From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34640) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RTZOv-0003IS-UV for qemu-devel@nongnu.org; Thu, 24 Nov 2011 08:31:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RTZOn-00053o-PH for qemu-devel@nongnu.org; Thu, 24 Nov 2011 08:31:41 -0500 Received: from mail-fx0-f45.google.com ([209.85.161.45]:44168) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RTZOn-00052Z-Hr for qemu-devel@nongnu.org; Thu, 24 Nov 2011 08:31:33 -0500 Received: by mail-fx0-f45.google.com with SMTP id s14so3156206faa.4 for ; Thu, 24 Nov 2011 05:31:33 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Thu, 24 Nov 2011 14:31:16 +0100 Message-Id: <1322141482-12173-6-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1322141482-12173-1-git-send-email-benoit.canet@gmail.com> References: <1322141482-12173-1-git-send-email-benoit.canet@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v4 05/11] lm32_uart: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoît Canet --- hw/lm32_uart.c | 31 +++++++++++++++---------------- 1 files changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c index 3678545..46a5ae0 100644 --- a/hw/lm32_uart.c +++ b/hw/lm32_uart.c @@ -91,6 +91,7 @@ enum { struct LM32UartState { SysBusDevice busdev; + MemoryRegion iomem; CharDriverState *chr; qemu_irq irq; @@ -124,7 +125,8 @@ static void uart_update_irq(LM32UartState *s) qemu_set_irq(s->irq, irq); } -static uint32_t uart_read(void *opaque, target_phys_addr_t addr) +static uint64_t uart_read(void *opaque, target_phys_addr_t addr, + unsigned size) { LM32UartState *s = opaque; uint32_t r = 0; @@ -158,7 +160,8 @@ static uint32_t uart_read(void *opaque, target_phys_addr_t addr) return r; } -static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) +static void uart_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { LM32UartState *s = opaque; unsigned char ch = value; @@ -192,16 +195,14 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) uart_update_irq(s); } -static CPUReadMemoryFunc * const uart_read_fn[] = { - NULL, - NULL, - &uart_read, -}; - -static CPUWriteMemoryFunc * const uart_write_fn[] = { - NULL, - NULL, - &uart_write, +static const MemoryRegionOps uart_ops = { + .read = uart_read, + .write = uart_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static void uart_rx(void *opaque, const uint8_t *buf, int size) @@ -245,13 +246,11 @@ static void uart_reset(DeviceState *d) static int lm32_uart_init(SysBusDevice *dev) { LM32UartState *s = FROM_SYSBUS(typeof(*s), dev); - int uart_regs; sysbus_init_irq(dev, &s->irq); - uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, R_MAX * 4, uart_regs); + memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4); + sysbus_init_mmio_region(dev, &s->iomem); s->chr = qdev_init_chardev(&dev->qdev); if (s->chr) { -- 1.7.7.3