From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:37358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RTwf4-0003S0-1K for qemu-devel@nongnu.org; Fri, 25 Nov 2011 09:21:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RTwez-00085o-IJ for qemu-devel@nongnu.org; Fri, 25 Nov 2011 09:21:53 -0500 Received: from mail-ww0-f53.google.com ([74.125.82.53]:37416) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RTwez-00084U-AF for qemu-devel@nongnu.org; Fri, 25 Nov 2011 09:21:49 -0500 Received: by mail-ww0-f53.google.com with SMTP id 10so3167603wwf.10 for ; Fri, 25 Nov 2011 06:21:48 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Fri, 25 Nov 2011 15:21:37 +0100 Message-Id: <1322230897-7470-6-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1322230897-7470-1-git-send-email-benoit.canet@gmail.com> References: <1322230897-7470-1-git-send-email-benoit.canet@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 5/5] omap_i2c: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoît Canet --- hw/omap.h | 7 +++++-- hw/omap1.c | 2 +- hw/omap_i2c.c | 45 +++++++++++++++++++++++++-------------------- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/hw/omap.h b/hw/omap.h index 837c73f..7ca8a42 100644 --- a/hw/omap.h +++ b/hw/omap.h @@ -770,8 +770,11 @@ void omap_mmc_enable(struct omap_mmc_s *s, int enable); /* omap_i2c.c */ struct omap_i2c_s; -struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, - qemu_irq irq, qemu_irq *dma, omap_clk clk); +struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem, + target_phys_addr_t base, + qemu_irq irq, + qemu_irq *dma, + omap_clk clk); struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); void omap_i2c_reset(struct omap_i2c_s *s); diff --git a/hw/omap1.c b/hw/omap1.c index f985f8d..53cde76 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -3964,7 +3964,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck")); omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck")); - s->i2c[0] = omap_i2c_init(0xfffb3800, + s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C), &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck")); diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c index 52c38ba..ca875f6 100644 --- a/hw/omap_i2c.c +++ b/hw/omap_i2c.c @@ -21,6 +21,7 @@ #include "omap.h" struct omap_i2c_s { + MemoryRegion iomem; qemu_irq irq; qemu_irq drq[2]; i2c_bus *bus; @@ -409,22 +410,28 @@ static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const omap_i2c_readfn[] = { - omap_badwidth_read16, - omap_i2c_read, - omap_badwidth_read16, +static const MemoryRegionOps omap_i2c_ops = { + .old_mmio = { + .read = { + omap_badwidth_read16, + omap_i2c_read, + omap_badwidth_read16, + }, + .write = { + omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */ + omap_i2c_write, + omap_badwidth_write16, + }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const omap_i2c_writefn[] = { - omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */ - omap_i2c_write, - omap_badwidth_write16, -}; - -struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, - qemu_irq irq, qemu_irq *dma, omap_clk clk) +struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem, + target_phys_addr_t base, + qemu_irq irq, + qemu_irq *dma, + omap_clk clk) { - int iomemtype; struct omap_i2c_s *s = (struct omap_i2c_s *) g_malloc0(sizeof(struct omap_i2c_s)); @@ -436,9 +443,8 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, s->bus = i2c_init_bus(NULL, "i2c"); omap_i2c_reset(s); - iomemtype = cpu_register_io_memory(omap_i2c_readfn, - omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x800, iomemtype); + memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", 0x800); + memory_region_add_subregion(sysmem, base, &s->iomem); return s; } @@ -446,7 +452,6 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk) { - int iomemtype; struct omap_i2c_s *s = (struct omap_i2c_s *) g_malloc0(sizeof(struct omap_i2c_s)); @@ -457,9 +462,9 @@ struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, s->bus = i2c_init_bus(NULL, "i2c"); omap_i2c_reset(s); - iomemtype = cpu_register_io_memory(omap_i2c_readfn, - omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN); - omap_l4_attach(ta, 0, iomemtype); + memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap2.i2c", + omap_l4_region_size(ta, 0)); + omap_l4_attach_region(ta, 0, &s->iomem); return s; } -- 1.7.7.3