* [Qemu-devel] [PATCH v2 1/5] omap_sx1: convert to memory API
2011-11-28 12:53 [Qemu-devel] [PATCH v2 0/5] convert some omap devices to memory API Benoît Canet
@ 2011-11-28 12:53 ` Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 2/5] omap_spi: " Benoît Canet
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Benoît Canet @ 2011-11-28 12:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/omap_sx1.c | 99 ++++++++++++++++++++++++++-------------------------------
1 files changed, 45 insertions(+), 54 deletions(-)
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index fe53545..8e58645 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -59,46 +59,28 @@
* - 1 RTC
*/
-static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
+static uint64_t static_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
uint32_t *val = (uint32_t *) opaque;
+ uint32_t mask = (4 / size) - 1;
- return *val >> ((offset & 3) << 3);
-}
-
-static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
-{
- uint32_t *val = (uint32_t *) opaque;
-
- return *val >> ((offset & 1) << 3);
-}
-
-static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
-{
- uint32_t *val = (uint32_t *) opaque;
-
- return *val >> ((offset & 0) << 3);
+ return *val >> ((offset & mask) << 3);
}
static void static_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
#ifdef SPY
- printf("%s: value %08lx written at " PA_FMT "\n",
- __FUNCTION__, value, offset);
+ printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n",
+ __func__, value, size, (int)offset);
#endif
}
-static CPUReadMemoryFunc * const static_readfn[] = {
- static_readb,
- static_readh,
- static_readw,
-};
-
-static CPUWriteMemoryFunc * const static_writefn[] = {
- static_write,
- static_write,
- static_write,
+static const MemoryRegionOps static_ops = {
+ .read = static_read,
+ .write = static_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#define sdram_size 0x02000000
@@ -123,7 +105,9 @@ static void sx1_init(ram_addr_t ram_size,
{
struct omap_mpu_state_s *cpu;
MemoryRegion *address_space = get_system_memory();
- int io;
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
+ MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
+ MemoryRegion *cs = g_new(MemoryRegion, 4);
static uint32_t cs0val = 0x00213090;
static uint32_t cs1val = 0x00215070;
static uint32_t cs2val = 0x00001139;
@@ -140,20 +124,25 @@ static void sx1_init(ram_addr_t ram_size,
cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
- cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
- qemu_ram_alloc(NULL, "omap_sx1.flash0-0",
- flash_size) | IO_MEM_ROM);
-
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
- OMAP_CS0_SIZE - flash_size, io);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
+ memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size);
+ memory_region_set_readonly(flash, true);
+ memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
+
+ memory_region_init_io(&cs[0], &static_ops, &cs0val,
+ "sx1.cs0", OMAP_CS0_SIZE - flash_size);
+ memory_region_add_subregion(address_space,
+ OMAP_CS0_BASE + flash_size, &cs[0]);
+
+
+ memory_region_init_io(&cs[2], &static_ops, &cs2val,
+ "sx1.cs2", OMAP_CS2_SIZE);
+ memory_region_add_subregion(address_space,
+ OMAP_CS2_BASE, &cs[2]);
+
+ memory_region_init_io(&cs[3], &static_ops, &cs3val,
+ "sx1.cs3", OMAP_CS3_SIZE);
+ memory_region_add_subregion(address_space,
+ OMAP_CS2_BASE, &cs[3]);
fl_idx = 0;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -176,13 +165,14 @@ static void sx1_init(ram_addr_t ram_size,
if ((version == 1) &&
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
- cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,
- qemu_ram_alloc(NULL, "omap_sx1.flash1-0",
- flash1_size) | IO_MEM_ROM);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
- OMAP_CS1_SIZE - flash1_size, io);
+ memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size);
+ memory_region_set_readonly(flash_1, true);
+ memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
+
+ memory_region_init_io(&cs[1], &static_ops, &cs1val,
+ "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
+ memory_region_add_subregion(address_space,
+ OMAP_CS1_BASE + flash1_size, &cs[1]);
if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL,
"omap_sx1.flash1-1", flash1_size,
@@ -194,9 +184,10 @@ static void sx1_init(ram_addr_t ram_size,
}
fl_idx++;
} else {
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
+ memory_region_init_io(&cs[1], &static_ops, &cs1val,
+ "sx1.cs1", OMAP_CS1_SIZE);
+ memory_region_add_subregion(address_space,
+ OMAP_CS1_BASE, &cs[1]);
}
if (!kernel_filename && !fl_idx) {
--
1.7.7.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PATCH v2 2/5] omap_spi: convert to memory API
2011-11-28 12:53 [Qemu-devel] [PATCH v2 0/5] convert some omap devices to memory API Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 1/5] omap_sx1: convert " Benoît Canet
@ 2011-11-28 12:53 ` Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 3/5] omap_lcdc: " Benoît Canet
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Benoît Canet @ 2011-11-28 12:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/omap_spi.c | 37 ++++++++++++++++++++-----------------
1 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/hw/omap_spi.c b/hw/omap_spi.c
index c20f425..4823bd0 100644
--- a/hw/omap_spi.c
+++ b/hw/omap_spi.c
@@ -24,6 +24,7 @@
/* Multichannel SPI */
struct omap_mcspi_s {
+ MemoryRegion iomem;
qemu_irq irq;
int chnum;
@@ -129,12 +130,17 @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
omap_mcspi_interrupt_update(s);
}
-static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
uint32_t ret;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* MCSPI_REVISION */
return 0x91;
@@ -199,11 +205,15 @@ static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* MCSPI_REVISION */
case 0x14: /* MCSPI_SYSSTATUS */
@@ -267,7 +277,7 @@ static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
if (((value >> 12) & 3) == 3) /* TRM */
fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
if (((value >> 7) & 0x1f) < 3) /* WL */
- fprintf(stderr, "%s: invalid WL value (%i)\n",
+ fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
__FUNCTION__, (value >> 7) & 0x1f);
s->ch[ch].config = value & 0x7fffff;
break;
@@ -298,22 +308,15 @@ static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_mcspi_read,
-};
-
-static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_mcspi_write,
+static const MemoryRegionOps omap_mcspi_ops = {
+ .read = omap_mcspi_read,
+ .write = omap_mcspi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
- int iomemtype;
struct omap_mcspi_s *s = (struct omap_mcspi_s *)
g_malloc0(sizeof(struct omap_mcspi_s));
struct omap_mcspi_ch_s *ch = s->ch;
@@ -327,9 +330,9 @@ struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
}
omap_mcspi_reset(s);
- iomemtype = cpu_register_io_memory(omap_mcspi_readfn,
- omap_mcspi_writefn, s, DEVICE_NATIVE_ENDIAN);
- omap_l4_attach(ta, 0, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mcspi_ops, s, "omap.mcspi",
+ omap_l4_region_size(ta, 0));
+ omap_l4_attach_region(ta, 0, &s->iomem);
return s;
}
--
1.7.7.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PATCH v2 3/5] omap_lcdc: convert to memory API
2011-11-28 12:53 [Qemu-devel] [PATCH v2 0/5] convert some omap devices to memory API Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 1/5] omap_sx1: convert " Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 2/5] omap_spi: " Benoît Canet
@ 2011-11-28 12:53 ` Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 4/5] omap_l4: " Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 5/5] omap_i2c: " Benoît Canet
4 siblings, 0 replies; 6+ messages in thread
From: Benoît Canet @ 2011-11-28 12:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/omap.h | 7 +++++--
hw/omap1.c | 2 +-
hw/omap_lcdc.c | 33 +++++++++++++++------------------
3 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index 759e90f..c04e683 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -732,8 +732,11 @@ void omap_tap_init(struct omap_target_agent_s *ta,
/* omap_lcdc.c */
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
-struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
- struct omap_dma_lcd_channel_s *dma, omap_clk clk);
+struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq,
+ struct omap_dma_lcd_channel_s *dma,
+ omap_clk clk);
/* omap_dss.c */
struct rfbi_chip_s {
diff --git a/hw/omap1.c b/hw/omap1.c
index 79b5178..f985f8d 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -3884,7 +3884,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
omap_findclk(s, "clk32-kHz"));
- s->lcd = omap_lcdc_init(0xfffec000,
+ s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
omap_dma_get_lcdch(s->dma),
omap_findclk(s, "lcd_ck"));
diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
index 29e6048..8484f70 100644
--- a/hw/omap_lcdc.c
+++ b/hw/omap_lcdc.c
@@ -22,6 +22,7 @@
#include "framebuffer.h"
struct omap_lcd_panel_s {
+ MemoryRegion iomem;
qemu_irq irq;
DisplayState *state;
@@ -323,7 +324,8 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
}
}
-static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_lcdc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -356,7 +358,7 @@ static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -399,16 +401,10 @@ static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_lcdc_readfn[] = {
- omap_lcdc_read,
- omap_lcdc_read,
- omap_lcdc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_lcdc_writefn[] = {
- omap_lcdc_write,
- omap_lcdc_write,
- omap_lcdc_write,
+static const MemoryRegionOps omap_lcdc_ops = {
+ .read = omap_lcdc_read,
+ .write = omap_lcdc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
void omap_lcdc_reset(struct omap_lcd_panel_s *s)
@@ -433,10 +429,12 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
s->ctrl = 0;
}
-struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
- struct omap_dma_lcd_channel_s *dma, omap_clk clk)
+struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq,
+ struct omap_dma_lcd_channel_s *dma,
+ omap_clk clk)
{
- int iomemtype;
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
g_malloc0(sizeof(struct omap_lcd_panel_s));
@@ -444,9 +442,8 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
s->dma = dma;
omap_lcdc_reset(s);
- iomemtype = cpu_register_io_memory(omap_lcdc_readfn,
- omap_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
s->state = graphic_console_init(omap_update_display,
omap_invalidate_display,
--
1.7.7.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PATCH v2 4/5] omap_l4: convert to memory API
2011-11-28 12:53 [Qemu-devel] [PATCH v2 0/5] convert some omap devices to memory API Benoît Canet
` (2 preceding siblings ...)
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 3/5] omap_lcdc: " Benoît Canet
@ 2011-11-28 12:53 ` Benoît Canet
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 5/5] omap_i2c: " Benoît Canet
4 siblings, 0 replies; 6+ messages in thread
From: Benoît Canet @ 2011-11-28 12:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/omap.h | 1 +
hw/omap_l4.c | 35 +++++++++++++++++++----------------
2 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index c04e683..837c73f 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -76,6 +76,7 @@ struct omap_l4_agent_info_s {
int ta_region;
};
struct omap_target_agent_s {
+ MemoryRegion iomem;
struct omap_l4_s *bus;
int regions;
const struct omap_l4_region_s *start;
diff --git a/hw/omap_l4.c b/hw/omap_l4.c
index a0bed5c..cf4b971 100644
--- a/hw/omap_l4.c
+++ b/hw/omap_l4.c
@@ -52,10 +52,15 @@ target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
return ta->start[region].size;
}
-static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_l4ta_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* COMPONENT */
return s->component;
@@ -72,10 +77,14 @@ static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
}
static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* COMPONENT */
case 0x28: /* AGENT_STATUS */
@@ -93,16 +102,10 @@ static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
- omap_badwidth_read16,
- omap_l4ta_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_l4ta_write,
+static const MemoryRegionOps omap_l4ta_ops = {
+ .read = omap_l4ta_read,
+ .write = omap_l4ta_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
@@ -110,7 +113,7 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
const struct omap_l4_agent_info_s *agents,
int cs)
{
- int i, iomemtype;
+ int i;
struct omap_target_agent_s *ta = NULL;
const struct omap_l4_agent_info_s *info = NULL;
@@ -133,9 +136,9 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
ta->status = 0x00000000;
ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
- iomemtype = cpu_register_io_memory(omap_l4ta_readfn,
- omap_l4ta_writefn, ta, DEVICE_NATIVE_ENDIAN);
- ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
+ memory_region_init_io(&ta->iomem, &omap_l4ta_ops, ta, "omap.l4ta",
+ omap_l4_region_size(ta, info->ta_region));
+ omap_l4_attach_region(ta, info->ta_region, &ta->iomem);
return ta;
}
--
1.7.7.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PATCH v2 5/5] omap_i2c: convert to memory API
2011-11-28 12:53 [Qemu-devel] [PATCH v2 0/5] convert some omap devices to memory API Benoît Canet
` (3 preceding siblings ...)
2011-11-28 12:53 ` [Qemu-devel] [PATCH v2 4/5] omap_l4: " Benoît Canet
@ 2011-11-28 12:53 ` Benoît Canet
4 siblings, 0 replies; 6+ messages in thread
From: Benoît Canet @ 2011-11-28 12:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/omap.h | 7 +++++--
hw/omap1.c | 2 +-
hw/omap_i2c.c | 45 +++++++++++++++++++++++++--------------------
3 files changed, 31 insertions(+), 23 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index 837c73f..7ca8a42 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -770,8 +770,11 @@ void omap_mmc_enable(struct omap_mmc_s *s, int enable);
/* omap_i2c.c */
struct omap_i2c_s;
-struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
- qemu_irq irq, qemu_irq *dma, omap_clk clk);
+struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq,
+ qemu_irq *dma,
+ omap_clk clk);
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
void omap_i2c_reset(struct omap_i2c_s *s);
diff --git a/hw/omap1.c b/hw/omap1.c
index f985f8d..53cde76 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -3964,7 +3964,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck"));
omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck"));
- s->i2c[0] = omap_i2c_init(0xfffb3800,
+ s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800,
qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
index 52c38ba..ca875f6 100644
--- a/hw/omap_i2c.c
+++ b/hw/omap_i2c.c
@@ -21,6 +21,7 @@
#include "omap.h"
struct omap_i2c_s {
+ MemoryRegion iomem;
qemu_irq irq;
qemu_irq drq[2];
i2c_bus *bus;
@@ -409,22 +410,28 @@ static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_i2c_readfn[] = {
- omap_badwidth_read16,
- omap_i2c_read,
- omap_badwidth_read16,
+static const MemoryRegionOps omap_i2c_ops = {
+ .old_mmio = {
+ .read = {
+ omap_badwidth_read16,
+ omap_i2c_read,
+ omap_badwidth_read16,
+ },
+ .write = {
+ omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
+ omap_i2c_write,
+ omap_badwidth_write16,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const omap_i2c_writefn[] = {
- omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
- omap_i2c_write,
- omap_badwidth_write16,
-};
-
-struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
- qemu_irq irq, qemu_irq *dma, omap_clk clk)
+struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq,
+ qemu_irq *dma,
+ omap_clk clk)
{
- int iomemtype;
struct omap_i2c_s *s = (struct omap_i2c_s *)
g_malloc0(sizeof(struct omap_i2c_s));
@@ -436,9 +443,8 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
- iomemtype = cpu_register_io_memory(omap_i2c_readfn,
- omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", 0x800);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
return s;
}
@@ -446,7 +452,6 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
{
- int iomemtype;
struct omap_i2c_s *s = (struct omap_i2c_s *)
g_malloc0(sizeof(struct omap_i2c_s));
@@ -457,9 +462,9 @@ struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
- iomemtype = cpu_register_io_memory(omap_i2c_readfn,
- omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
- omap_l4_attach(ta, 0, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap2.i2c",
+ omap_l4_region_size(ta, 0));
+ omap_l4_attach_region(ta, 0, &s->iomem);
return s;
}
--
1.7.7.3
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