From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53047) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXhs1-000277-Q5 for qemu-devel@nongnu.org; Mon, 05 Dec 2011 18:22:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RXhrz-00031o-L4 for qemu-devel@nongnu.org; Mon, 05 Dec 2011 18:22:49 -0500 Received: from cantor2.suse.de ([195.135.220.15]:36451 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXhrz-00031U-DJ for qemu-devel@nongnu.org; Mon, 05 Dec 2011 18:22:47 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 6 Dec 2011 00:21:18 +0100 Message-Id: <1323127282-20306-6-git-send-email-afaerber@suse.de> In-Reply-To: <1323127282-20306-1-git-send-email-afaerber@suse.de> References: <1323127282-20306-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 5/9] target-arm: Infer AUXCR feature from ARMv6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Andreas F=C3=A4rber V6 =3D> AUXCR Note that this newly enables AUXCR for Cortex-M3. Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- target-arm/helper.c | 6 +----- 1 files changed, 1 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index caee25c..7b52792 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -84,7 +84,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32= _t id) */ set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); /* These ID register values are correct for 1136 but may be wron= g * for 1136_r2 (in particular r0p2 does not actually implement m= ost * of the ID registers). @@ -100,7 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint3= 2_t id) case ARM_CPUID_ARM1176: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; @@ -113,7 +111,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) case ARM_CPUID_ARM11MPCORE: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] =3D 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] =3D 0x11111111; @@ -124,7 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) break; case ARM_CPUID_CORTEXA8: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -144,7 +140,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -244,6 +239,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); + set_feature(env, ARM_FEATURE_AUXCR); } if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); --=20 1.7.7