From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53263) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXiws-0005JR-95 for qemu-devel@nongnu.org; Mon, 05 Dec 2011 19:31:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RXiwq-0007gZ-Cu for qemu-devel@nongnu.org; Mon, 05 Dec 2011 19:31:54 -0500 Received: from mout.web.de ([212.227.15.3]:56421) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXiwq-0007g9-0k for qemu-devel@nongnu.org; Mon, 05 Dec 2011 19:31:52 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 6 Dec 2011 01:30:40 +0100 Message-Id: <1323131446-21864-4-git-send-email-andreas.faerber@web.de> In-Reply-To: <1323131446-21864-1-git-send-email-andreas.faerber@web.de> References: <1323131446-21864-1-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 3/9] target-arm: Infer ARMv6 feature from v6K List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= V6K => V6 Signed-off-by: Andreas Färber Cc: Peter Maydell --- target-arm/helper.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index b8b6921..109918b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -98,7 +98,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); @@ -112,7 +111,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); @@ -125,7 +123,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_AUXCR); @@ -147,7 +144,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_AUXCR); @@ -181,7 +177,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_THUMB2); @@ -243,6 +238,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); } + if (arm_feature(env, ARM_FEATURE_V6K)) { + set_feature(env, ARM_FEATURE_V6); + } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); } -- 1.7.7