From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53286) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXiwt-0005Pc-Uo for qemu-devel@nongnu.org; Mon, 05 Dec 2011 19:31:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RXiws-0007hL-9r for qemu-devel@nongnu.org; Mon, 05 Dec 2011 19:31:55 -0500 Received: from mout.web.de ([212.227.15.3]:56430) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXiwr-0007gv-Qw for qemu-devel@nongnu.org; Mon, 05 Dec 2011 19:31:54 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 6 Dec 2011 01:30:42 +0100 Message-Id: <1323131446-21864-6-git-send-email-andreas.faerber@web.de> In-Reply-To: <1323131446-21864-1-git-send-email-andreas.faerber@web.de> References: <1323131446-21864-1-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 5/9] target-arm: Infer AUXCR feature from ARMv6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= V6 && !M => AUXCR Signed-off-by: Andreas Färber Cc: Peter Maydell --- target-arm/helper.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index caee25c..0db8872 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -84,7 +84,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); /* These ID register values are correct for 1136 but may be wrong * for 1136_r2 (in particular r0p2 does not actually implement most * of the ID registers). @@ -100,7 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM1176: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; @@ -113,7 +111,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM11MPCORE: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; @@ -124,7 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA8: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -144,7 +140,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -244,6 +239,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); + if (!arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_AUXCR); + } } if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); -- 1.7.7