[Qemu-devel] [RFC 0/6] target-i386: TCGv cleanups

[Qemu-devel] [RFC 0/6] target-i386: TCGv cleanups

[Andreas Färber]

Hello,

This series makes target-i386 compile with DEBUG_TCGV_TL.

Patches 1-2 could be cherry-picked already.

Patch 1 is fairly trivial.
Patch 2 is the only patch in the series that needs an additional temporary.
Patch 3 introduces two new functions to avoid that elsewhere. Needs TCGv series.

With that, patch 4 then becomes as trivial as patch 1.

Patches 5-6 convert x86_64-specific code to match generic code, switching to
a pre-existing temporary from the preceding if branch, and add missing braces.

Regards,
Andreas

Andreas Färber (6):
  target-i386: Fix sloppy uses of i32/i64 functions
  target-i386: Cleanup movd xmm, ea
  tcg: Add tcg_gen_qemu_{ld,st}64_tl()
  target-i386: Use tcg_gen_{ld,st}64_tl()
  target-i386: Cleanup pinsrq
  target-i386: Cleanup pextrq

 target-i386/translate.c |  174 ++++++++++++++++++++++++-----------------------
 tcg/tcg-op.h            |   12 +++
 2 files changed, 102 insertions(+), 84 deletions(-)

-- 
1.7.7

[Qemu-devel] [PATCH 1/6] target-i386: Fix sloppy uses of i32/i64 functions

[Andreas Färber]

Use TCGv (tl) versions instead.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 target-i386/translate.c |  130 +++++++++++++++++++++++-----------------------
 1 files changed, 65 insertions(+), 65 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1ef8d16..0ffc450 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3351,8 +3351,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x7e: /* movd ea, mm */
 #ifdef TARGET_X86_64
             if (s->dflag == 2) {
-                tcg_gen_ld_i64(cpu_T[0], cpu_env, 
-                               offsetof(CPUX86State,fpregs[reg].mmx));
+                tcg_gen_ld_tl(cpu_T[0], cpu_env, 
+                              offsetof(CPUX86State,fpregs[reg].mmx));
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
             } else
 #endif
@@ -3365,8 +3365,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x17e: /* movd ea, xmm */
 #ifdef TARGET_X86_64
             if (s->dflag == 2) {
-                tcg_gen_ld_i64(cpu_T[0], cpu_env, 
-                               offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+                tcg_gen_ld_tl(cpu_T[0], cpu_env, 
+                              offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
             } else
 #endif
@@ -4427,14 +4427,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     t0 = tcg_temp_new_i64();
                     t1 = tcg_temp_new_i64();
                     gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
-                    tcg_gen_extu_i32_i64(t0, cpu_T[0]);
-                    tcg_gen_extu_i32_i64(t1, cpu_T[1]);
+                    tcg_gen_extu_tl_i64(t0, cpu_T[0]);
+                    tcg_gen_extu_tl_i64(t1, cpu_T[1]);
                     tcg_gen_mul_i64(t0, t0, t1);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EAX);
                     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
                     tcg_gen_shri_i64(t0, t0, 32);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EDX);
                     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
                 }
@@ -4496,15 +4496,15 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     t0 = tcg_temp_new_i64();
                     t1 = tcg_temp_new_i64();
                     gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
-                    tcg_gen_ext_i32_i64(t0, cpu_T[0]);
-                    tcg_gen_ext_i32_i64(t1, cpu_T[1]);
+                    tcg_gen_ext_tl_i64(t0, cpu_T[0]);
+                    tcg_gen_ext_tl_i64(t1, cpu_T[1]);
                     tcg_gen_mul_i64(t0, t0, t1);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EAX);
                     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
                     tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
                     tcg_gen_shri_i64(t0, t0, 32);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EDX);
                     tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
                 }
@@ -4789,14 +4789,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     TCGv_i64 t0, t1;
                     t0 = tcg_temp_new_i64();
                     t1 = tcg_temp_new_i64();
-                    tcg_gen_ext_i32_i64(t0, cpu_T[0]);
-                    tcg_gen_ext_i32_i64(t1, cpu_T[1]);
+                    tcg_gen_ext_tl_i64(t0, cpu_T[0]);
+                    tcg_gen_ext_tl_i64(t1, cpu_T[1]);
                     tcg_gen_mul_i64(t0, t0, t1);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
                     tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
                     tcg_gen_shri_i64(t0, t0, 32);
-                    tcg_gen_trunc_i64_i32(cpu_T[1], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[1], t0);
                     tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
                 }
 #endif
@@ -6772,7 +6772,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 #ifdef TARGET_X86_64
         if (dflag == 2) {
             gen_op_mov_TN_reg(OT_QUAD, 0, reg);
-            tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
+            tcg_gen_bswap64_tl(cpu_T[0], cpu_T[0]);
             gen_op_mov_reg_T0(OT_QUAD, reg);
         } else
 #endif
@@ -7650,55 +7650,55 @@ void optimize_flags_init(void)
                                     "cc_tmp");
 
 #ifdef TARGET_X86_64
-    cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EAX]), "rax");
-    cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ECX]), "rcx");
-    cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDX]), "rdx");
-    cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBX]), "rbx");
-    cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESP]), "rsp");
-    cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBP]), "rbp");
-    cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESI]), "rsi");
-    cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDI]), "rdi");
-    cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
-                                         offsetof(CPUState, regs[8]), "r8");
-    cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[9]), "r9");
-    cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[10]), "r10");
-    cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[11]), "r11");
-    cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[12]), "r12");
-    cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[13]), "r13");
-    cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[14]), "r14");
-    cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[15]), "r15");
+    cpu_regs[R_EAX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EAX]), "rax");
+    cpu_regs[R_ECX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ECX]), "rcx");
+    cpu_regs[R_EDX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDX]), "rdx");
+    cpu_regs[R_EBX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBX]), "rbx");
+    cpu_regs[R_ESP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESP]), "rsp");
+    cpu_regs[R_EBP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBP]), "rbp");
+    cpu_regs[R_ESI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESI]), "rsi");
+    cpu_regs[R_EDI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDI]), "rdi");
+    cpu_regs[8] = tcg_global_mem_new(TCG_AREG0,
+                                     offsetof(CPUState, regs[8]), "r8");
+    cpu_regs[9] = tcg_global_mem_new(TCG_AREG0,
+                                     offsetof(CPUState, regs[9]), "r9");
+    cpu_regs[10] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[10]), "r10");
+    cpu_regs[11] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[11]), "r11");
+    cpu_regs[12] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[12]), "r12");
+    cpu_regs[13] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[13]), "r13");
+    cpu_regs[14] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[14]), "r14");
+    cpu_regs[15] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[15]), "r15");
 #else
-    cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EAX]), "eax");
-    cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ECX]), "ecx");
-    cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDX]), "edx");
-    cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBX]), "ebx");
-    cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESP]), "esp");
-    cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBP]), "ebp");
-    cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESI]), "esi");
-    cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDI]), "edi");
+    cpu_regs[R_EAX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EAX]), "eax");
+    cpu_regs[R_ECX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ECX]), "ecx");
+    cpu_regs[R_EDX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDX]), "edx");
+    cpu_regs[R_EBX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBX]), "ebx");
+    cpu_regs[R_ESP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESP]), "esp");
+    cpu_regs[R_EBP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBP]), "ebp");
+    cpu_regs[R_ESI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESI]), "esi");
+    cpu_regs[R_EDI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDI]), "edi");
 #endif
 
     /* register helpers */
-- 
1.7.7

[Qemu-devel] [PATCH 2/6] target-i386: Cleanup movd xmm, ea

[Andreas Färber]

Insert call to tcg_gen_ext_tl_i64().

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 target-i386/translate.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 0ffc450..c929ef9 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3192,10 +3192,14 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x16e: /* movd xmm, ea */
 #ifdef TARGET_X86_64
             if (s->dflag == 2) {
+                TCGv_i64 tmp;
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
                                  offsetof(CPUX86State,xmm_regs[reg]));
-                gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
+                tmp = tcg_temp_new_i64();
+                tcg_gen_ext_tl_i64(tmp, cpu_T[0]);
+                gen_helper_movq_mm_T0_xmm(cpu_ptr0, tmp);
+                tcg_temp_free_i64(tmp);
             } else
 #endif
             {
-- 
1.7.7

[Qemu-devel] [RFC 3/6] tcg: Add tcg_gen_qemu_{ld,st}64_tl()

[Andreas Färber]

Encapsule the conversion from/to i64.
This avoids a temporary and a tcg_gen_trunc_i64_tl()/ext_tl_i64().

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 tcg/tcg-op.h |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index d065e74..07c6d3e 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -3217,6 +3217,18 @@ static inline void tcg_gen_deposit_tl(TCGv ret, TCGv arg1, TCGv arg2,
 #endif
 }
 
+#if TARGET_LONG_BITS == 64
+static inline void tcg_gen_qemu_ld64_tl(TCGv ret, TCGv addr, int mem_index)
+{
+    tcg_gen_qemu_ld64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), addr, mem_index);
+}
+
+static inline void tcg_gen_qemu_st64_tl(TCGv arg, TCGv addr, int mem_index)
+{
+    tcg_gen_qemu_st64(MAKE_TCGV_I64(GET_TCGV_TL(arg)), addr, mem_index);
+}
+#endif
+
 static inline TCGv tcg_const_tl(tcg_target_long val)
 {
 #if TARGET_LONG_BITS == 64
-- 
1.7.7

[Qemu-devel] [RFC 4/6] target-i386: Use tcg_gen_{ld,st}64_tl()

[Andreas Färber]

Use new helper function to avoid new temporaries and moves.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 target-i386/translate.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index c929ef9..17465e9 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -525,7 +525,7 @@ static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
     case 3:
         /* Should never happen on 32-bit targets.  */
 #ifdef TARGET_X86_64
-        tcg_gen_qemu_ld64(t0, a0, mem_index);
+        tcg_gen_qemu_ld64_tl(t0, a0, mem_index);
 #endif
         break;
     }
@@ -564,7 +564,7 @@ static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
     case 3:
         /* Should never happen on 32-bit targets.  */
 #ifdef TARGET_X86_64
-        tcg_gen_qemu_st64(t0, a0, mem_index);
+        tcg_gen_qemu_st64_tl(t0, a0, mem_index);
 #endif
         break;
     }
-- 
1.7.7

[Qemu-devel] [RFC 5/6] target-i386: Cleanup pinsrq

[Andreas Färber]

gen_op_mov_v_reg() wants a TCGv, so use cpu_tmp0 like pinsrd does.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 target-i386/translate.c |   17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 17465e9..6d09496 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3916,14 +3916,15 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                                                 xmm_regs[reg].XMM_L(val & 3)));
                     } else { /* pinsrq */
 #ifdef TARGET_X86_64
-                        if (mod == 3)
-                            gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
-                        else
-                            tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
-                                            (s->mem_index >> 2) - 1);
-                        tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
-                                        offsetof(CPUX86State,
-                                                xmm_regs[reg].XMM_Q(val & 1)));
+                        if (mod == 3) {
+                            gen_op_mov_v_reg(ot, cpu_tmp0, rm);
+                        } else {
+                            tcg_gen_qemu_ld64_tl(cpu_tmp0, cpu_A0,
+                                                 (s->mem_index >> 2) - 1);
+                        }
+                        tcg_gen_st_tl(cpu_tmp0, cpu_env,
+                                      offsetof(CPUX86State,
+                                               xmm_regs[reg].XMM_Q(val & 1)));
 #else
                         goto illegal_op;
 #endif
-- 
1.7.7

[Qemu-devel] [RFC 6/6] target-i386: Cleanup pextrq

[Andreas Färber]

gen_op_mov_reg_v() wants a TCGv, so use cpu_T[0] like pextrd does.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 target-i386/translate.c |   17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6d09496..5ce8d3e 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3842,14 +3842,15 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                                             (s->mem_index >> 2) - 1);
                     } else { /* pextrq */
 #ifdef TARGET_X86_64
-                        tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
-                                        offsetof(CPUX86State,
-                                                xmm_regs[reg].XMM_Q(val & 1)));
-                        if (mod == 3)
-                            gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
-                        else
-                            tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
-                                            (s->mem_index >> 2) - 1);
+                        tcg_gen_ld_tl(cpu_T[0], cpu_env,
+                                      offsetof(CPUX86State,
+                                               xmm_regs[reg].XMM_Q(val & 1)));
+                        if (mod == 3) {
+                            gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+                        } else {
+                            tcg_gen_qemu_st64_tl(cpu_T[0], cpu_A0,
+                                                 (s->mem_index >> 2) - 1);
+                        }
 #else
                         goto illegal_op;
 #endif
-- 
1.7.7

Re: [Qemu-devel] [RFC 0/6] target-i386: TCGv cleanups

[Paul Brook]

> This series makes target-i386 compile with DEBUG_TCGV_TL.

What benefit does this provide?

I effectively already asked this in reply to your patch adding 
DEBUG_TCGV_TL[1].  One answer is sufficient, this mail is really just to link 
the two threads together :-)

Paul

[1] http://lists.nongnu.org/archive/html/qemu-devel/2011-12/msg01261.html

Re: [Qemu-devel] [RFC 0/6] target-i386: TCGv cleanups

[Andreas Färber]

Am 12.12.2011 00:42, schrieb Paul Brook:
>> This series makes target-i386 compile with DEBUG_TCGV_TL.
> 
> What benefit does this provide?

It showcases what changes would need to be done to allow type-safe
compilation of the first pair of --enable-system targets.

Especially my focus has been on how to do that without introducing loads
of unnecessary temporaries.

Andreas

Re: [Qemu-devel] [RFC 0/6] target-i386: TCGv cleanups

[Paul Brook]

> Am 12.12.2011 00:42, schrieb Paul Brook:
> >> This series makes target-i386 compile with DEBUG_TCGV_TL.
> > 
> > What benefit does this provide?
> 
> It showcases what changes would need to be done to allow type-safe
> compilation of the first pair of --enable-system targets.

How is the existing code not type safe?  What benefit does making TCGv a 
separate type rather than an alias for either _i32 or _i64 give?

Paul

Re: [Qemu-devel] [RFC 0/6] target-i386: TCGv cleanups

[Andreas Färber]

Am 12.12.2011 15:56, schrieb Paul Brook:
>> Am 12.12.2011 00:42, schrieb Paul Brook:
>>>> This series makes target-i386 compile with DEBUG_TCGV_TL.
>>>
>>> What benefit does this provide?
>>
>> It showcases what changes would need to be done to allow type-safe
>> compilation of the first pair of --enable-system targets.
> 
> How is the existing code not type safe?  What benefit does making TCGv a 
> separate type rather than an alias for either _i32 or _i64 give?

I've already answered that extensively elsewhere.

Look, I really personally don't care about i386 and whether this RFC
gets applied to target-i386 or not. This is an example, because the
changes that I *do* care about have already been folded into my branch,
with the help of my TCGv series now posted for others' benefit.

Please read the other thread for details of what it does and doesn't do.

Andreas