From: Evgeny Voevodin <e.voevodin@samsung.com>
To: qemu-devel@nongnu.org
Cc: m.kozlov@samsung.com, d.solodkiy@samsung.com,
Evgeny Voevodin <e.voevodin@samsung.com>
Subject: [Qemu-devel] [PATCH v3 10/14] hw/lan9118: Add basic 16-bit mode support.
Date: Mon, 12 Dec 2011 10:43:22 +0400 [thread overview]
Message-ID: <1323672206-11891-11-git-send-email-e.voevodin@samsung.com> (raw)
In-Reply-To: <1323672206-11891-1-git-send-email-e.voevodin@samsung.com>
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
---
hw/devices.h | 2 +-
hw/lan9118.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++++++++----
2 files changed, 109 insertions(+), 8 deletions(-)
diff --git a/hw/devices.h b/hw/devices.h
index 1a55c1e..24cae4c 100644
--- a/hw/devices.h
+++ b/hw/devices.h
@@ -10,7 +10,7 @@ struct MemoryRegion;
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
/* lan9118.c */
-void lan9118_init(NICInfo *, uint32_t, qemu_irq);
+DeviceState *lan9118_init(NICInfo *, uint32_t, qemu_irq);
/* tsc210x.c */
uWireSlave *tsc2102_init(qemu_irq pint);
diff --git a/hw/lan9118.c b/hw/lan9118.c
index ee8b2ea..e44e5f8 100644
--- a/hw/lan9118.c
+++ b/hw/lan9118.c
@@ -212,6 +212,17 @@ typedef struct {
int rxp_offset;
int rxp_size;
int rxp_pad;
+
+ uint32_t write_word_prev_offset;
+ uint32_t write_word_n;
+ uint16_t write_word_l;
+ uint16_t write_word_h;
+ uint32_t read_word_prev_offset;
+ uint32_t read_word_n;
+ uint32_t read_long;
+
+ uint32_t mode_16bit;
+
} lan9118_state;
static void lan9118_update(lan9118_state *s)
@@ -345,6 +356,9 @@ static void lan9118_reset(DeviceState *d)
s->mac_mii_data = 0;
s->mac_flow = 0;
+ s->read_word_n = 0;
+ s->write_word_n = 0;
+
phy_reset(s);
s->eeprom_writable = 0;
@@ -896,11 +910,11 @@ static void lan9118_tick(void *opaque)
}
static void lan9118_writel(void *opaque, target_phys_addr_t offset,
- uint64_t val, unsigned size)
+ uint32_t val)
{
lan9118_state *s = (lan9118_state *)opaque;
offset &= 0xff;
-
+
//DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
if (offset >= 0x20 && offset < 0x40) {
/* TX FIFO */
@@ -1029,8 +1043,47 @@ static void lan9118_writel(void *opaque, target_phys_addr_t offset,
lan9118_update(s);
}
-static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
- unsigned size)
+static void lan9118_writew(void *opaque, target_phys_addr_t offset,
+ uint32_t val)
+{
+ lan9118_state *s = (lan9118_state *)opaque;
+ offset &= 0xff;
+
+ if (s->write_word_prev_offset != (offset & ~0x3)) {
+ /* New offset, reset word counter */
+ s->write_word_n = 0;
+ s->write_word_prev_offset = offset & ~0x3;
+ }
+
+ if (offset & 0x2) {
+ s->write_word_h = val;
+ } else {
+ s->write_word_l = val;
+ }
+
+ //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val);
+ s->write_word_n++;
+ if (s->write_word_n == 2) {
+ s->write_word_n = 0;
+ lan9118_writel(s, offset & ~3, s->write_word_l +
+ (s->write_word_h << 16));
+ }
+}
+
+static void lan9118_write(void *opaque, target_phys_addr_t offset,
+ uint64_t val, unsigned size)
+{
+ switch (size) {
+ case 2:
+ return lan9118_writew(opaque, offset, (uint32_t)val);
+ case 4:
+ return lan9118_writel(opaque, offset, (uint32_t)val);
+ }
+
+ hw_error("lan9118_write: Bad size 0x%x\n", size);
+}
+
+static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset)
{
lan9118_state *s = (lan9118_state *)opaque;
@@ -1065,6 +1118,9 @@ static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
case CSR_TX_CFG:
return s->tx_cfg;
case CSR_HW_CFG:
+ if (s->mode_16bit) {
+ return s->hw_cfg & ~0x4;
+ }
return s->hw_cfg | 0x4;
case CSR_RX_DP_CTRL:
return 0;
@@ -1103,9 +1159,51 @@ static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
return 0;
}
+static uint32_t lan9118_readw(void *opaque, target_phys_addr_t offset)
+{
+ lan9118_state *s = (lan9118_state *)opaque;
+ uint32_t val;
+
+ if (s->read_word_prev_offset != (offset & ~0x3)) {
+ /* New offset, reset word counter */
+ s->read_word_n = 0;
+ s->read_word_prev_offset = offset & ~0x3;
+ }
+
+ s->read_word_n++;
+ if (s->read_word_n == 1) {
+ s->read_long = lan9118_readl(s, offset & ~3);
+ } else {
+ s->read_word_n = 0;
+ }
+
+ if (offset & 2) {
+ val = s->read_long >> 16;
+ } else {
+ val = s->read_long & 0xFFFF;
+ }
+
+ //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val);
+ return val;
+}
+
+static uint64_t lan9118_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
+{
+ switch (size) {
+ case 2:
+ return lan9118_readw(opaque, offset);
+ case 4:
+ return lan9118_readl(opaque, offset);
+ }
+
+ hw_error("lan9118_read: Bad size 0x%x\n", size);
+ return 0;
+}
+
static const MemoryRegionOps lan9118_mem_ops = {
- .read = lan9118_readl,
- .write = lan9118_writel,
+ .read = lan9118_read,
+ .write = lan9118_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
@@ -1162,6 +1260,7 @@ static SysBusDeviceInfo lan9118_info = {
.qdev.reset = lan9118_reset,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(lan9118_state, conf),
+ DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0),
DEFINE_PROP_END_OF_LIST(),
}
};
@@ -1173,7 +1272,7 @@ static void lan9118_register_devices(void)
/* Legacy helper function. Should go away when machine config files are
implemented. */
-void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
+DeviceState *lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
@@ -1185,6 +1284,8 @@ void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
s = sysbus_from_qdev(dev);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
+
+ return dev;
}
device_init(lan9118_register_devices)
--
1.7.4.1
next prev parent reply other threads:[~2011-12-12 6:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-12 6:43 [Qemu-devel] [PATCH v3 00/14] ARM: Samsung Exynos4210-based boards support Evgeny Voevodin
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 01/14] ARM: Samsung exynos4210-based boards emulation Evgeny Voevodin
2011-12-12 22:17 ` Peter Maydell
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 02/14] ARM: exynos4210: CMU support Evgeny Voevodin
2011-12-12 22:44 ` Peter Maydell
2011-12-14 12:10 ` Maksim E. Kozlov
2011-12-14 11:43 ` Peter Maydell
2011-12-14 17:08 ` Maksim E. Kozlov
2011-12-14 16:25 ` Peter Maydell
2011-12-15 7:11 ` Dmitry Solodkiy
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 03/14] ARM: exynos4210: UART support Evgeny Voevodin
2011-12-12 22:55 ` Peter Maydell
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 04/14] hw/sysbus.h: Increase maximum number of device IRQs Evgeny Voevodin
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 05/14] ARM: exynos4210: IRQ subsystem support Evgeny Voevodin
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 06/14] ARM: exynos4210: PWM support Evgeny Voevodin
2011-12-13 10:51 ` Peter Maydell
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 07/14] hw/arm_boot.c: Add new secondary CPU bootloader Evgeny Voevodin
2011-12-13 11:28 ` Peter Maydell
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 08/14] ARM: exynos4210: MCT support Evgeny Voevodin
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 09/14] hw/exynos4210.c: Boot secondary CPU Evgeny Voevodin
2011-12-12 6:43 ` Evgeny Voevodin [this message]
2011-12-13 11:54 ` [Qemu-devel] [PATCH v3 10/14] hw/lan9118: Add basic 16-bit mode support Peter Maydell
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 11/14] hw/exynos4210.c: Add LAN support for SMDKC210 Evgeny Voevodin
2011-12-13 12:01 ` Peter Maydell
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 12/14] hw/sd.c, hw/sd.h: add receive ready query routine to SD/MMC API Evgeny Voevodin
2011-12-13 15:11 ` Peter Maydell
2011-12-13 16:22 ` Peter Maydell
2011-12-14 8:29 ` Mitsyanko Igor
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 13/14] ARM: exynos4210: added SD/MMC host controller Evgeny Voevodin
2011-12-13 14:56 ` Peter Maydell
2011-12-13 16:23 ` Mitsyanko Igor
2011-12-12 6:43 ` [Qemu-devel] [PATCH v3 14/14] ARM: exynos4210: added display controller implementation Evgeny Voevodin
2011-12-12 7:22 ` [Qemu-devel] [PATCH v3 00/14] ARM: Samsung Exynos4210-based boards support Stefan Weil
2011-12-13 10:14 ` Peter Maydell
2011-12-13 10:37 ` Dmitry Solodkiy
2011-12-13 10:59 ` Peter Maydell
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