From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ra3QW-0003pj-Kx for qemu-devel@nongnu.org; Mon, 12 Dec 2011 05:48:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ra3QQ-00069O-1m for qemu-devel@nongnu.org; Mon, 12 Dec 2011 05:48:08 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:45674) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ra3QP-000684-P7 for qemu-devel@nongnu.org; Mon, 12 Dec 2011 05:48:02 -0500 From: Peter Maydell Date: Mon, 12 Dec 2011 10:47:45 +0000 Message-Id: <1323686869-15567-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1323686869-15567-1-git-send-email-peter.maydell@linaro.org> References: <1323686869-15567-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 4/8] hw/mpcore.c: Use the GIC memory regions for the CPU interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org Switch to using the GIC memory regions for the CPU interface rather than hand implementing them as a subcase of mpcore_priv_read() and mpcore_priv_write(). Signed-off-by: Peter Maydell --- hw/mpcore.c | 35 ++++++++++------------------------- 1 files changed, 10 insertions(+), 25 deletions(-) diff --git a/hw/mpcore.c b/hw/mpcore.c index 3d64609..a0af1ad 100644 --- a/hw/mpcore.c +++ b/hw/mpcore.c @@ -41,7 +41,7 @@ static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset, { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; - offset &= 0xfff; + offset &= 0xff; if (offset < 0x100) { /* SCU */ switch (offset) { @@ -57,17 +57,6 @@ static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset, default: goto bad_reg; } - } else if (offset < 0x600) { - /* Interrupt controller. */ - if (offset < 0x200) { - id = gic_get_current_cpu(); - } else { - id = (offset - 0x200) >> 8; - if (id >= s->num_cpu) { - return 0; - } - } - return gic_cpu_read(&s->gic, id, offset & 0xff); } bad_reg: hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); @@ -78,8 +67,7 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; - int id; - offset &= 0xfff; + offset &= 0xff; if (offset < 0x100) { /* SCU */ switch (offset) { @@ -92,16 +80,6 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, default: goto bad_reg; } - } else if (offset < 0x600) { - /* Interrupt controller. */ - if (offset < 0x200) { - id = gic_get_current_cpu(); - } else { - id = (offset - 0x200) >> 8; - } - if (id < s->num_cpu) { - gic_cpu_write(&s->gic, id, offset & 0xff, value); - } } return; bad_reg: @@ -129,8 +107,15 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s) SysBusDevice *busdev = sysbus_from_qdev(s->mptimer); memory_region_init(&s->container, "mpcode-priv-container", 0x2000); memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv", - 0x1000); + 0x100); memory_region_add_subregion(&s->container, 0, &s->iomem); + /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs + * at 0x200, 0x300... + */ + for (i = 0; i < (s->num_cpu + 1); i++) { + target_phys_addr_t offset = 0x100 + (i * 0x100); + memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]); + } /* Add the regions for timer and watchdog for "current CPU" and * for each specific CPU. */ -- 1.7.1