From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ra3Qi-0004Fm-Pu for qemu-devel@nongnu.org; Mon, 12 Dec 2011 05:48:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ra3QQ-00069l-SE for qemu-devel@nongnu.org; Mon, 12 Dec 2011 05:48:15 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:45674) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ra3QQ-000684-Jh for qemu-devel@nongnu.org; Mon, 12 Dec 2011 05:48:02 -0500 From: Peter Maydell Date: Mon, 12 Dec 2011 10:47:47 +0000 Message-Id: <1323686869-15567-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1323686869-15567-1-git-send-email-peter.maydell@linaro.org> References: <1323686869-15567-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 6/8] hw/mpcore: Clean up mpcore_priv_read/write as they are now SCU only List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org The only code left in mpcore_priv_read and mpcore_priv_write is now the implementation of the SCU registers. Clean up by renaming functions and removing some unnecessary conditionals to make this clearer. Signed-off-by: Peter Maydell --- hw/mpcore.c | 73 +++++++++++++++++++++++++---------------------------------- 1 files changed, 31 insertions(+), 42 deletions(-) diff --git a/hw/mpcore.c b/hw/mpcore.c index a0af1ad..670d7e5 100644 --- a/hw/mpcore.c +++ b/hw/mpcore.c @@ -36,59 +36,49 @@ typedef struct mpcore_priv_state { /* Per-CPU private memory mapped IO. */ -static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset, - unsigned size) +static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset, + unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; offset &= 0xff; - if (offset < 0x100) { - /* SCU */ - switch (offset) { - case 0x00: /* Control. */ - return s->scu_control; - case 0x04: /* Configuration. */ - id = ((1 << s->num_cpu) - 1) << 4; - return id | (s->num_cpu - 1); - case 0x08: /* CPU status. */ - return 0; - case 0x0c: /* Invalidate all. */ - return 0; - default: - goto bad_reg; - } + /* SCU */ + switch (offset) { + case 0x00: /* Control. */ + return s->scu_control; + case 0x04: /* Configuration. */ + id = ((1 << s->num_cpu) - 1) << 4; + return id | (s->num_cpu - 1); + case 0x08: /* CPU status. */ + return 0; + case 0x0c: /* Invalidate all. */ + return 0; + default: + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); } -bad_reg: - hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); - return 0; } -static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, - uint64_t value, unsigned size) +static void mpcore_scu_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; offset &= 0xff; - if (offset < 0x100) { - /* SCU */ - switch (offset) { - case 0: /* Control register. */ - s->scu_control = value & 1; - break; - case 0x0c: /* Invalidate all. */ - /* This is a no-op as cache is not emulated. */ - break; - default: - goto bad_reg; - } + /* SCU */ + switch (offset) { + case 0: /* Control register. */ + s->scu_control = value & 1; + break; + case 0x0c: /* Invalidate all. */ + /* This is a no-op as cache is not emulated. */ + break; + default: + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); } - return; -bad_reg: - hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); } -static const MemoryRegionOps mpcore_priv_ops = { - .read = mpcore_priv_read, - .write = mpcore_priv_write, +static const MemoryRegionOps mpcore_scu_ops = { + .read = mpcore_scu_read, + .write = mpcore_scu_write, .endianness = DEVICE_NATIVE_ENDIAN, }; @@ -106,8 +96,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s) int i; SysBusDevice *busdev = sysbus_from_qdev(s->mptimer); memory_region_init(&s->container, "mpcode-priv-container", 0x2000); - memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv", - 0x100); + memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); memory_region_add_subregion(&s->container, 0, &s->iomem); /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs * at 0x200, 0x300... -- 1.7.1