From: zanghongyong@huawei.com
To: qemu-devel@nongnu.org, kvm@vger.kernel.org
Cc: wusongwei@huawei.com, hanweidong@huawei.com,
louzhengwei@huawei.com, xiaowei.yang@huawei.com,
zanghongyong@huawei.com, avi@redhat.com, cam@cs.ualberta.ca
Subject: [Qemu-devel] [PATCH v3 2/3] ivshmem: add a new PIO BAR4(Doorbell) to reduce notification time
Date: Tue, 13 Dec 2011 09:42:47 +0800 [thread overview]
Message-ID: <1323740568-17692-3-git-send-email-zanghongyong@huawei.com> (raw)
In-Reply-To: <1323740568-17692-1-git-send-email-zanghongyong@huawei.com>
From: Hongyong Zang <zanghongyong@huawei.com>
This patch adds a PIO BAR4 for guest notifying qemu to reduce notification time.
And the new notification way of PIO BAR4 reduces 30% time in comparison with the
original MMIO BAR0 way.
Also, this patch introduces a new feature named IVSHMEM_PIO_NOTIFY to make PIO
BAR4 disappeared for compatible with machine type pc-1.0 or blow.
Signed-off-by: Hongyong Zang <zanghongyong@huawei.com>
---
hw/ivshmem.c | 34 ++++++++++++++++++++++++++++++++--
hw/pc_piix.c | 28 ++++++++++++++++++++++++++++
2 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index 80b5db0..6845ade 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -26,11 +26,13 @@
#define IVSHMEM_IOEVENTFD 0
#define IVSHMEM_MSI 1
+#define IVSHMEM_PIO_NOTIFY 2
#define IVSHMEM_PEER 0
#define IVSHMEM_MASTER 1
#define IVSHMEM_REG_BAR_SIZE 0x100
+#define IVSHIO_REG_BAR_SIZE 0x10
//#define DEBUG_IVSHMEM
#ifdef DEBUG_IVSHMEM
@@ -59,6 +61,7 @@ typedef struct IVShmemState {
CharDriverState **eventfd_chr;
CharDriverState *server_chr;
MemoryRegion ivshmem_mmio;
+ MemoryRegion ivshmem_pio;
/* We might need to register the BAR before we actually have the memory.
* So prepare a container MemoryRegion for the BAR immediately and
@@ -237,7 +240,7 @@ static uint64_t ivshmem_io_read(void *opaque, target_phys_addr_t addr,
return ret;
}
-static const MemoryRegionOps ivshmem_mmio_ops = {
+static const MemoryRegionOps ivshmem_io_ops = {
.read = ivshmem_io_read,
.write = ivshmem_io_write,
.endianness = DEVICE_NATIVE_ENDIAN,
@@ -356,6 +359,14 @@ static void close_guest_eventfds(IVShmemState *s, int posn)
true,
(posn << 16) | i,
s->peers[posn].eventfds[i]);
+ if(ivshmem_has_feature(s, IVSHMEM_PIO_NOTIFY)) {
+ memory_region_del_eventfd(&s->ivshmem_pio,
+ DOORBELL,
+ 4,
+ true,
+ (posn << 16) | i,
+ s->peers[posn].eventfds[i]);
+ }
}
close(s->peers[posn].eventfds[i]);
}
@@ -490,6 +501,14 @@ static void ivshmem_read(void *opaque, const uint8_t * buf, int flags)
true,
(incoming_posn << 16) | guest_max_eventfd,
incoming_fd);
+ if(ivshmem_has_feature(s, IVSHMEM_PIO_NOTIFY)) {
+ memory_region_add_eventfd(&s->ivshmem_pio,
+ DOORBELL,
+ 4,
+ true,
+ (incoming_posn << 16) | guest_max_eventfd,
+ incoming_fd);
+ }
}
return;
@@ -652,13 +671,20 @@ static int pci_ivshmem_init(PCIDevice *dev)
s->shm_fd = 0;
- memory_region_init_io(&s->ivshmem_mmio, &ivshmem_mmio_ops, s,
+ memory_region_init_io(&s->ivshmem_mmio, &ivshmem_io_ops, s,
"ivshmem-mmio", IVSHMEM_REG_BAR_SIZE);
/* region for registers*/
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->ivshmem_mmio);
+ if(ivshmem_has_feature(s, IVSHMEM_PIO_NOTIFY)) {
+ memory_region_init_io(&s->ivshmem_pio, &ivshmem_io_ops, s,
+ "ivshmem-pio", IVSHIO_REG_BAR_SIZE);
+ pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO,
+ &s->ivshmem_pio);
+ }
+
memory_region_init(&s->bar, "ivshmem-bar2-container", s->ivshmem_size);
if ((s->server_chr != NULL) &&
@@ -738,6 +764,9 @@ static int pci_ivshmem_uninit(PCIDevice *dev)
error_free(s->migration_blocker);
}
+ if(ivshmem_has_feature(s, IVSHMEM_PIO_NOTIFY)) {
+ memory_region_destroy(&s->ivshmem_pio);
+ }
memory_region_destroy(&s->ivshmem_mmio);
memory_region_del_subregion(&s->bar, &s->ivshmem);
memory_region_destroy(&s->ivshmem);
@@ -762,6 +791,7 @@ static PCIDeviceInfo ivshmem_info = {
DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, false),
DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
+ DEFINE_PROP_BIT("pio_notify", IVShmemState, features, IVSHMEM_PIO_NOTIFY, true),
DEFINE_PROP_STRING("shm", IVShmemState, shmobj),
DEFINE_PROP_STRING("role", IVShmemState, role),
DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 970f43c..fe64874 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -304,6 +304,14 @@ static QEMUMachine pc_machine_v1_0 = {
.init = pc_init_pci,
.max_cpus = 255,
.is_default = 1,
+ .compat_props = (GlobalProperty[]) {
+ {
+ .driver = "ivshmem",
+ .property = "pio_notify",
+ .value = "off",
+ },
+ { /* end of list */ }
+ },
};
static QEMUMachine pc_machine_v0_14 = {
@@ -320,6 +328,10 @@ static QEMUMachine pc_machine_v0_14 = {
.driver = "qxl-vga",
.property = "revision",
.value = stringify(2),
+ },{
+ .driver = "ivshmem",
+ .property = "pio_notify",
+ .value = "off",
},
{ /* end of list */ }
},
@@ -363,6 +375,10 @@ static QEMUMachine pc_machine_v0_13 = {
.driver = "AC97",
.property = "use_broken_id",
.value = stringify(1),
+ },{
+ .driver = "ivshmem",
+ .property = "pio_notify",
+ .value = "off",
},
{ /* end of list */ }
},
@@ -410,6 +426,10 @@ static QEMUMachine pc_machine_v0_12 = {
.driver = "AC97",
.property = "use_broken_id",
.value = stringify(1),
+ },{
+ .driver = "ivshmem",
+ .property = "pio_notify",
+ .value = "off",
},
{ /* end of list */ }
}
@@ -465,6 +485,10 @@ static QEMUMachine pc_machine_v0_11 = {
.driver = "AC97",
.property = "use_broken_id",
.value = stringify(1),
+ },{
+ .driver = "ivshmem",
+ .property = "pio_notify",
+ .value = "off",
},
{ /* end of list */ }
}
@@ -532,6 +556,10 @@ static QEMUMachine pc_machine_v0_10 = {
.driver = "AC97",
.property = "use_broken_id",
.value = stringify(1),
+ },{
+ .driver = "ivshmem",
+ .property = "pio_notify",
+ .value = "off",
},
{ /* end of list */ }
},
--
1.7.1
next prev parent reply other threads:[~2011-12-13 2:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-13 1:42 [Qemu-devel] [PATCH v3 0/3] ivshmem: add a new PIO BAR4(Doorbell) besides MMIO BAR0 to reduce notification time zanghongyong
2011-12-13 1:42 ` [Qemu-devel] [PATCH v3 1/3] memory: add a memory API about ioeventfd for PIO long zanghongyong
2011-12-13 1:42 ` zanghongyong [this message]
2011-12-13 1:42 ` [Qemu-devel] [PATCH v3 3/3] ivshmem: update the spec zanghongyong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1323740568-17692-3-git-send-email-zanghongyong@huawei.com \
--to=zanghongyong@huawei.com \
--cc=avi@redhat.com \
--cc=cam@cs.ualberta.ca \
--cc=hanweidong@huawei.com \
--cc=kvm@vger.kernel.org \
--cc=louzhengwei@huawei.com \
--cc=qemu-devel@nongnu.org \
--cc=wusongwei@huawei.com \
--cc=xiaowei.yang@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).