* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2011-12-13 18:30 Peter Maydell
2011-12-13 18:30 ` [Qemu-devel] [PATCH 01/10] arm: Fix CP15 FSR (C5) domain setting Peter Maydell
` (10 more replies)
0 siblings, 11 replies; 32+ messages in thread
From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Paul Brook, qemu-devel
Current target-arm pending patches; mostly these are Andreas'
inference series, plus one from Jean-Christophe that's been
waiting since before the 1.0 release.
Please pull.
-- PMM
The following changes since commit da5361cc685c004d8bb4e7c5e7b3a52c7aca2c56:
ccid: make threads joinable (2011-12-12 17:06:22 -0600)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
Andreas Färber (9):
target-arm: Infer ARMv4T feature from ARMv5
target-arm: Infer ARMv5 feature from ARMv6
target-arm: Infer ARMv6 feature from v6K
target-arm: Infer ARMv6(K) feature from ARMv7
target-arm: Infer AUXCR feature from ARMv6
target-arm: Infer Thumb2 feature from ARMv7
target-arm: Infer Thumb division feature from M profile
target-arm: Infer VFP feature from VFPv3
target-arm: Infer VFPv3 feature from VFPv4
Jean-Christophe DUBOIS (1):
arm: Fix CP15 FSR (C5) domain setting
target-arm/helper.c | 95 ++++++++++++++++++++++----------------------------
1 files changed, 42 insertions(+), 53 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH 01/10] arm: Fix CP15 FSR (C5) domain setting 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 02/10] target-arm: Infer ARMv4T feature from ARMv5 Peter Maydell ` (9 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Jean-Christophe DUBOIS <jcd@tribudubois.net> Return the correct value in the domain field in the cp15 DFSR (C5) -- bug noticed during Xvisor development. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> [Peter Maydell: reworded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 26 +++++++++++++++----------- 1 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3fe5822..1949202 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -951,13 +951,14 @@ void do_interrupt(CPUARMState *env) /* Check section/page access permissions. Returns the page protection flags, or zero if the access is not permitted. */ -static inline int check_ap(CPUState *env, int ap, int domain, int access_type, - int is_user) +static inline int check_ap(CPUState *env, int ap, int domain_prot, + int access_type, int is_user) { int prot_ro; - if (domain == 3) + if (domain_prot == 3) { return PAGE_READ | PAGE_WRITE; + } if (access_type == 1) prot_ro = 0; @@ -1023,6 +1024,7 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, int type; int ap; int domain; + int domain_prot; uint32_t phys_addr; /* Pagetable walk. */ @@ -1030,13 +1032,14 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, table = get_level1_table_address(env, address); desc = ldl_phys(table); type = (desc & 3); - domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; + domain = (desc >> 5) & 0x0f; + domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; if (type == 0) { /* Section translation fault. */ code = 5; goto do_fault; } - if (domain == 0 || domain == 2) { + if (domain_prot == 0 || domain_prot == 2) { if (type == 2) code = 9; /* Section domain fault. */ else @@ -1094,7 +1097,7 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, } code = 15; } - *prot = check_ap(env, ap, domain, access_type, is_user); + *prot = check_ap(env, ap, domain_prot, access_type, is_user); if (!*prot) { /* Access permission fault. */ goto do_fault; @@ -1117,6 +1120,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, int type; int ap; int domain; + int domain_prot; uint32_t phys_addr; /* Pagetable walk. */ @@ -1134,10 +1138,10 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, domain = 0; } else { /* Section or page. */ - domain = (desc >> 4) & 0x1e; + domain = (desc >> 5) & 0x0f; } - domain = (env->cp15.c3 >> domain) & 3; - if (domain == 0 || domain == 2) { + domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; + if (domain_prot == 0 || domain_prot == 2) { if (type == 2) code = 9; /* Section domain fault. */ else @@ -1182,7 +1186,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, } code = 15; } - if (domain == 3) { + if (domain_prot == 3) { *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (xn && access_type == 2) @@ -1194,7 +1198,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, code = (code == 15) ? 6 : 3; goto do_fault; } - *prot = check_ap(env, ap, domain, access_type, is_user); + *prot = check_ap(env, ap, domain_prot, access_type, is_user); if (!*prot) { /* Access permission fault. */ goto do_fault; -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 02/10] target-arm: Infer ARMv4T feature from ARMv5 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 01/10] arm: Fix CP15 FSR (C5) domain setting Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 03/10] target-arm: Infer ARMv5 feature from ARMv6 Peter Maydell ` (8 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> V5 => V4T Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 15 +++------------ 1 files changed, 3 insertions(+), 12 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1949202..eff2ac1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -53,7 +53,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cpuid = id; switch (id) { case ARM_CPUID_ARM926: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_VFP); env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; @@ -61,14 +60,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_MPU); env->cp15.c0_cachetype = 0x0f004006; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); @@ -85,7 +82,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) * older core than plain "arm1136". In particular this does not * have the v6K features. */ - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); @@ -103,7 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); @@ -119,7 +114,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); @@ -134,7 +128,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); @@ -158,7 +151,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); @@ -187,7 +179,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_THUMB2); @@ -196,7 +187,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); @@ -226,7 +216,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA260: case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_XSCALE); /* JTAG_ID is ((id << 28) | 0x09265013) */ @@ -239,7 +228,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: - set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_XSCALE); /* JTAG_ID is ((id << 28) | 0x09265013) */ @@ -262,6 +250,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); } + if (arm_feature(env, ARM_FEATURE_V5)) { + set_feature(env, ARM_FEATURE_V4T); + } if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { set_feature(env, ARM_FEATURE_THUMB_DIV); } -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 03/10] target-arm: Infer ARMv5 feature from ARMv6 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 01/10] arm: Fix CP15 FSR (C5) domain setting Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 02/10] target-arm: Infer ARMv4T feature from ARMv5 Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 04/10] target-arm: Infer ARMv6 feature from v6K Peter Maydell ` (7 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> V6 => V5 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 10 +++------- 1 files changed, 3 insertions(+), 7 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index eff2ac1..6a78dd0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -82,7 +82,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) * older core than plain "arm1136". In particular this does not * have the v6K features. */ - set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); @@ -99,7 +98,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); @@ -114,7 +112,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); @@ -128,7 +125,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); @@ -151,7 +147,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); @@ -179,7 +174,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: - set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_V7); @@ -187,7 +181,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ - set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); @@ -250,6 +243,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); } + if (arm_feature(env, ARM_FEATURE_V6)) { + set_feature(env, ARM_FEATURE_V5); + } if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 04/10] target-arm: Infer ARMv6 feature from v6K 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (2 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 03/10] target-arm: Infer ARMv5 feature from ARMv6 Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 05/10] target-arm: Infer ARMv6(K) feature from ARMv7 Peter Maydell ` (6 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> V6K => V6 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6a78dd0..a948b88 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -98,7 +98,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); @@ -112,7 +111,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); @@ -125,7 +123,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_AUXCR); @@ -147,7 +144,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_AUXCR); @@ -181,7 +177,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_THUMB2); @@ -243,6 +238,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); } + if (arm_feature(env, ARM_FEATURE_V6K)) { + set_feature(env, ARM_FEATURE_V6); + } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); } -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 05/10] target-arm: Infer ARMv6(K) feature from ARMv7 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (3 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 04/10] target-arm: Infer ARMv6 feature from v6K Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 06/10] target-arm: Infer AUXCR feature from ARMv6 Peter Maydell ` (5 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> V7 && M => V6 V7 && !M => V6K Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index a948b88..1108156 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -123,7 +123,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); @@ -144,7 +143,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); @@ -170,14 +168,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: - set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_M); set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ - set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); @@ -237,6 +233,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); + if (!arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_V6K); + } else { + set_feature(env, ARM_FEATURE_V6); + } } if (arm_feature(env, ARM_FEATURE_V6K)) { set_feature(env, ARM_FEATURE_V6); -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 06/10] target-arm: Infer AUXCR feature from ARMv6 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (4 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 05/10] target-arm: Infer ARMv6(K) feature from ARMv7 Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 07/10] target-arm: Infer Thumb2 feature from ARMv7 Peter Maydell ` (4 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> V6 && !M => AUXCR Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1108156..0a7f745 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -84,7 +84,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); /* These ID register values are correct for 1136 but may be wrong * for 1136_r2 (in particular r0p2 does not actually implement most * of the ID registers). @@ -100,7 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM1176: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; @@ -113,7 +111,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM11MPCORE: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; @@ -124,7 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA8: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -144,7 +140,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -244,6 +239,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); + if (!arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_AUXCR); + } } if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 07/10] target-arm: Infer Thumb2 feature from ARMv7 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (5 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 06/10] target-arm: Infer AUXCR feature from ARMv6 Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 08/10] target-arm: Infer Thumb division feature from M profile Peter Maydell ` (3 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> V7 => THUMB2 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 0a7f745..281b315 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -121,7 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA8: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_NEON); @@ -140,7 +139,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP_FP16); @@ -163,14 +161,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: - set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_M); set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP4); @@ -228,6 +224,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); + set_feature(env, ARM_FEATURE_THUMB2); if (!arm_feature(env, ARM_FEATURE_M)) { set_feature(env, ARM_FEATURE_V6K); } else { -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 08/10] target-arm: Infer Thumb division feature from M profile 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (6 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 07/10] target-arm: Infer Thumb2 feature from ARMv7 Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 09/10] target-arm: Infer VFP feature from VFPv3 Peter Maydell ` (2 subsequent siblings) 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> M => THUMB_DIV Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 281b315..a566aa3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -163,7 +163,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_CORTEXM3: set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_M); - set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ set_feature(env, ARM_FEATURE_V7); @@ -243,6 +242,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } + if (arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_THUMB_DIV); + } if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { set_feature(env, ARM_FEATURE_THUMB_DIV); } -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 09/10] target-arm: Infer VFP feature from VFPv3 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (7 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 08/10] target-arm: Infer Thumb division feature from M profile Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 10/10] target-arm: Infer VFPv3 feature from VFPv4 Peter Maydell 2011-12-14 20:41 ` [Qemu-devel] [PULL 00/10] target-arm queue andrzej zaborowski 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> VFP3 => VFP Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index a566aa3..bd5576c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -121,7 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA8: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_NEON); set_feature(env, ARM_FEATURE_THUMB2EE); @@ -139,7 +138,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP_FP16); set_feature(env, ARM_FEATURE_NEON); @@ -166,7 +164,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_ANY: /* For userspace emulation. */ set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP4); set_feature(env, ARM_FEATURE_VFP_FP16); @@ -248,6 +245,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { set_feature(env, ARM_FEATURE_THUMB_DIV); } + if (arm_feature(env, ARM_FEATURE_VFP3)) { + set_feature(env, ARM_FEATURE_VFP); + } } void cpu_reset(CPUARMState *env) -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 10/10] target-arm: Infer VFPv3 feature from VFPv4 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (8 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 09/10] target-arm: Infer VFP feature from VFPv3 Peter Maydell @ 2011-12-13 18:30 ` Peter Maydell 2011-12-14 20:41 ` [Qemu-devel] [PULL 00/10] target-arm queue andrzej zaborowski 10 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw) To: Anthony Liguori; +Cc: Paul Brook, qemu-devel From: Andreas Färber <andreas.faerber@web.de> VFP4 => VFP3 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index bd5576c..65f4fbf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -164,7 +164,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_ANY: /* For userspace emulation. */ set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP4); set_feature(env, ARM_FEATURE_VFP_FP16); set_feature(env, ARM_FEATURE_NEON); @@ -245,6 +244,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { set_feature(env, ARM_FEATURE_THUMB_DIV); } + if (arm_feature(env, ARM_FEATURE_VFP4)) { + set_feature(env, ARM_FEATURE_VFP3); + } if (arm_feature(env, ARM_FEATURE_VFP3)) { set_feature(env, ARM_FEATURE_VFP); } -- 1.7.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell ` (9 preceding siblings ...) 2011-12-13 18:30 ` [Qemu-devel] [PATCH 10/10] target-arm: Infer VFPv3 feature from VFPv4 Peter Maydell @ 2011-12-14 20:41 ` andrzej zaborowski 10 siblings, 0 replies; 32+ messages in thread From: andrzej zaborowski @ 2011-12-14 20:41 UTC (permalink / raw) To: Peter Maydell; +Cc: Anthony Liguori, Paul Brook, qemu-devel On 13 December 2011 19:30, Peter Maydell <peter.maydell@linaro.org> wrote: > Current target-arm pending patches; mostly these are Andreas' > inference series, plus one from Jean-Christophe that's been > waiting since before the 1.0 release. > > Please pull. Thanks, pulled (and pushed) Cheers ^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2014-05-01 14:54 Peter Maydell
2014-05-02 11:11 ` Peter Maydell
2014-05-04 18:30 ` Richard W.M. Jones
0 siblings, 2 replies; 32+ messages in thread
From: Peter Maydell @ 2014-05-01 14:54 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
Nothing earthshattering here, but it does have the patch which
actually lets us boot an emulated AArch64 CPU on a board...
thanks
-- PMM
The following changes since commit 051b9980b99dbfba22ea5f79bd3708d513ae121d:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-6' into staging (2014-05-01 14:17:33 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140501
for you to fetch changes up to f42c5c8ec8aa0e15583487ffee62964830751623:
hw/arm/virt: Add support for Cortex-A57 (2014-05-01 15:25:52 +0100)
----------------------------------------------------------------
target-arm queue:
* implement XScale cache lockdown cp15 ops
* fix v7M CPUID base register
* implement WFE and YIELD as yields for A64
* fix A64 "BLR LR"
* support Cortex-A57 in virt machine model
* a few other minor AArch64 bugfixes
----------------------------------------------------------------
Edgar E. Iglesias (4):
target-arm: Make vbar_write 64bit friendly on 32bit hosts
target-arm: A64: Handle blr lr
target-arm: A64: Fix a typo when declaring TLBI ops
target-arm: Correct a comment refering to EL0
Peter Maydell (4):
target-arm: Implement XScale cache lockdown operations as NOPs
hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv
hw/arm/virt: Put GIC register banks on 64K boundaries
hw/arm/virt: Add support for Cortex-A57
Rabin Vincent (1):
armv7m_nvic: fix CPUID Base Register
Rob Herring (1):
target-arm: implement WFE/YIELD as a yield for AArch64
hw/arm/virt.c | 93 ++++++++++++++++++++++++++++++----------------
hw/intc/armv7m_nvic.c | 2 +-
target-arm/helper.c | 41 +++++++++++++-------
target-arm/op_helper.c | 2 +-
target-arm/translate-a64.c | 9 ++++-
5 files changed, 99 insertions(+), 48 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-01 14:54 Peter Maydell @ 2014-05-02 11:11 ` Peter Maydell 2014-05-04 18:30 ` Richard W.M. Jones 1 sibling, 0 replies; 32+ messages in thread From: Peter Maydell @ 2014-05-02 11:11 UTC (permalink / raw) To: Anthony Liguori; +Cc: QEMU Developers On 1 May 2014 15:54, Peter Maydell <peter.maydell@linaro.org> wrote: > Nothing earthshattering here, but it does have the patch which > actually lets us boot an emulated AArch64 CPU on a board... > > thanks > -- PMM > > The following changes since commit 051b9980b99dbfba22ea5f79bd3708d513ae121d: > > Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-6' into staging (2014-05-01 14:17:33 +0100) > > are available in the git repository at: > > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140501 > > for you to fetch changes up to f42c5c8ec8aa0e15583487ffee62964830751623: > > hw/arm/virt: Add support for Cortex-A57 (2014-05-01 15:25:52 +0100) Applied, thanks. -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-01 14:54 Peter Maydell 2014-05-02 11:11 ` Peter Maydell @ 2014-05-04 18:30 ` Richard W.M. Jones 2014-05-04 18:48 ` Peter Maydell 1 sibling, 1 reply; 32+ messages in thread From: Richard W.M. Jones @ 2014-05-04 18:30 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, Anthony Liguori On Thu, May 01, 2014 at 03:54:57PM +0100, Peter Maydell wrote: > Nothing earthshattering here, but it does have the patch which > actually lets us boot an emulated AArch64 CPU on a board... Hi Peter, I have real aarch64 hardware, and I'm trying to find a version of qemu-system-aarch64 which will boot a KVM guest in some form. Upstream qemu fails with a bizarre thread-local storage problem (yes, I've patched glibc to fix the makecontext problem). Is there a qemu tree I should be looking at? Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming and virtualization blog: http://rwmj.wordpress.com virt-p2v converts physical machines to virtual machines. Boot with a live CD or over the network (PXE) and turn machines into KVM guests. http://libguestfs.org/virt-v2v ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-04 18:30 ` Richard W.M. Jones @ 2014-05-04 18:48 ` Peter Maydell 2014-05-04 18:58 ` Richard W.M. Jones 2014-05-04 19:29 ` Richard W.M. Jones 0 siblings, 2 replies; 32+ messages in thread From: Peter Maydell @ 2014-05-04 18:48 UTC (permalink / raw) To: Richard W.M. Jones; +Cc: QEMU Developers, Anthony Liguori On 4 May 2014 19:30, Richard W.M. Jones <rjones@redhat.com> wrote: > I have real aarch64 hardware, and I'm trying to find a version of > qemu-system-aarch64 which will boot a KVM guest in some form. > > Upstream qemu fails with a bizarre thread-local storage problem (yes, > I've patched glibc to fix the makecontext problem). > > Is there a qemu tree I should be looking at? Upstream is it. I haven't been testing it for a while though; it's possible it bitrotted while I wasn't looking. thanks -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-04 18:48 ` Peter Maydell @ 2014-05-04 18:58 ` Richard W.M. Jones 2014-05-04 19:36 ` Peter Maydell 2014-05-04 19:29 ` Richard W.M. Jones 1 sibling, 1 reply; 32+ messages in thread From: Richard W.M. Jones @ 2014-05-04 18:58 UTC (permalink / raw) To: Peter Maydell; +Cc: QEMU Developers, Anthony Liguori On Sun, May 04, 2014 at 07:48:38PM +0100, Peter Maydell wrote: > On 4 May 2014 19:30, Richard W.M. Jones <rjones@redhat.com> wrote: > > I have real aarch64 hardware, and I'm trying to find a version of > > qemu-system-aarch64 which will boot a KVM guest in some form. > > > > Upstream qemu fails with a bizarre thread-local storage problem (yes, > > I've patched glibc to fix the makecontext problem). > > > > Is there a qemu tree I should be looking at? > > Upstream is it. I haven't been testing it for a while though; it's possible > it bitrotted while I wasn't looking. OK, it might be a kernel problem then. This was the issue I was having before: /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 \ -global virtio-blk-device.scsi=off \ -nodefconfig \ -enable-fips \ -nodefaults \ -display none \ -M virt \ -machine accel=kvm:tcg \ -m 500 \ -no-reboot \ -rtc driftfix=slew \ -global kvm-pit.lost_tick_policy=discard \ -kernel /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/kernel \ -initrd /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/initrd \ -device virtio-scsi-device,id=scsi \ -drive file=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/scratch.1,cache=unsafe,format=raw,id=hd0,if=none \ -device scsi-hd,drive=hd0 \ -drive file=/home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/root,snapshot=on,id=appliance,cache=unsafe,if=none \ -device scsi-hd,drive=appliance \ -device virtio-serial-device \ -serial stdio \ -chardev socket,path=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/guestfsd.sock,id=channel0 \ -device virtserialport,chardev=channel0,name=org.libguestfs.channel.0 \ -append 'panic=1 console=ttyS0 udevtimeout=600 no_timer_check acpi=off printk.time=1 cgroup_disable=memory root=/dev/sdb selinux=0 guestfs_verbose=1 TERM=screen' Could not access KVM kernel module: Permission denied failed to initialize KVM: Permission denied Back to tcg accelerator. libguestfs: error: appliance closed the connection unexpectedly, see earlier error messages libguestfs: child_cleanup: 0x3b5a1770: child process died libguestfs: sending SIGTERM to process 12438 libguestfs: error: /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 killed by signal 11 (Segmentation fault), see debug messages above The stack trace in qemu when the segfault occurs is: Program terminated with signal SIGSEGV, Segmentation fault. #0 0x000002aae2f17394 in cpu_arm_exec (env=0x3ff8401eed0, env@entry=0x2ab1c978440) at /home/rjones/d/qemu/cpu-exec.c:241 241 current_cpu = cpu; (gdb) print tls__current_cpu Cannot find thread-local storage for LWP 12922, executable file /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64: TLS not supported on this target ... and ^^^ that's the part that makes no sense to me. TLS must surely be supported, so there must be something odd about the compile-time environment. Linux ***.redhat.com 3.13.0-0.rc7.31.***.aarch64.debug #1 SMP Fri May 2 16:55:22 EDT 2014 aarch64 aarch64 aarch64 GNU/Linux glibc-2.19.90-11.fc21.aarch64 gcc-4.9.0-1.fc21.aarch64 Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming and virtualization blog: http://rwmj.wordpress.com virt-df lists disk usage of guests without needing to install any software inside the virtual machine. Supports Linux and Windows. http://people.redhat.com/~rjones/virt-df/ ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-04 18:58 ` Richard W.M. Jones @ 2014-05-04 19:36 ` Peter Maydell 2014-05-04 19:45 ` Richard W.M. Jones 0 siblings, 1 reply; 32+ messages in thread From: Peter Maydell @ 2014-05-04 19:36 UTC (permalink / raw) To: Richard W.M. Jones; +Cc: QEMU Developers, Anthony Liguori On 4 May 2014 19:58, Richard W.M. Jones <rjones@redhat.com> wrote: > On Sun, May 04, 2014 at 07:48:38PM +0100, Peter Maydell wrote: >> On 4 May 2014 19:30, Richard W.M. Jones <rjones@redhat.com> wrote: >> > I have real aarch64 hardware, and I'm trying to find a version of >> > qemu-system-aarch64 which will boot a KVM guest in some form. >> > >> > Upstream qemu fails with a bizarre thread-local storage problem (yes, >> > I've patched glibc to fix the makecontext problem). >> > >> > Is there a qemu tree I should be looking at? >> >> Upstream is it. I haven't been testing it for a while though; it's possible >> it bitrotted while I wasn't looking. > > OK, it might be a kernel problem then. > > This was the issue I was having before: > > /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 \ > -global virtio-blk-device.scsi=off \ > -nodefconfig \ > -enable-fips \ > -nodefaults \ > -display none \ > -M virt \ > -machine accel=kvm:tcg \ > -m 500 \ > -no-reboot \ > -rtc driftfix=slew \ > -global kvm-pit.lost_tick_policy=discard \ > -kernel /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/kernel \ > -initrd /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/initrd \ > -device virtio-scsi-device,id=scsi \ > -drive file=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/scratch.1,cache=unsafe,format=raw,id=hd0,if=none \ > -device scsi-hd,drive=hd0 \ > -drive file=/home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/root,snapshot=on,id=appliance,cache=unsafe,if=none \ > -device scsi-hd,drive=appliance \ > -device virtio-serial-device \ > -serial stdio \ > -chardev socket,path=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/guestfsd.sock,id=channel0 \ > -device virtserialport,chardev=channel0,name=org.libguestfs.channel.0 \ > -append 'panic=1 console=ttyS0 udevtimeout=600 no_timer_check acpi=off printk.time=1 cgroup_disable=memory root=/dev/sdb selinux=0 guestfs_verbose=1 TERM=screen' > Could not access KVM kernel module: Permission denied > failed to initialize KVM: Permission denied > Back to tcg accelerator. OK, so you have a kernel (possibly just kernel config) problem here -- this means QEMU got EPERM trying to open /dev/kvm. This isn't going to work for aarch64 at the moment because: * KVM aarch64 currently requires '-cpu host' * '-cpu host' is a KVM only thing that won't work with TCG If you don't enable KVM we don't put 'host' in the CPU list so usually the TCG code can't see it -- however "use KVM but have the init fail" is a path I hadn't considered for getting into TCG with -cpu host. Does this happen if you start with accel=tcg so we're using TCG all the way through? You can also ignore all this in favour of just figuring out why your kernel didn't let us open /dev/kvm... PS: I didn't see a "-cpu something" in your command line; I forget what the default is but it's probably not what you want. > libguestfs: error: appliance closed the connection unexpectedly, see earlier error messages > libguestfs: child_cleanup: 0x3b5a1770: child process died > libguestfs: sending SIGTERM to process 12438 > libguestfs: error: /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 killed by signal 11 (Segmentation fault), see debug messages above > > The stack trace in qemu when the segfault occurs is: > > Program terminated with signal SIGSEGV, Segmentation fault. > #0 0x000002aae2f17394 in cpu_arm_exec (env=0x3ff8401eed0, > env@entry=0x2ab1c978440) at /home/rjones/d/qemu/cpu-exec.c:241 > 241 current_cpu = cpu; > > (gdb) print tls__current_cpu > Cannot find thread-local storage for LWP 12922, executable file /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64: > TLS not supported on this target > > ... and ^^^ that's the part that makes no sense to me. TLS must > surely be supported, so there must be something odd about the > compile-time environment. I think that message is gdb saying that it doesn't support TLS, not that the target architecture doesn't support TLS. How ancient is your gdb? Google suggests that TLS support went into the aarch64 target somewhat after the initial architecture support (though still a year or so ago, so I would have expected it to get in...) thanks -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-04 19:36 ` Peter Maydell @ 2014-05-04 19:45 ` Richard W.M. Jones 2014-05-04 19:55 ` Peter Maydell 0 siblings, 1 reply; 32+ messages in thread From: Richard W.M. Jones @ 2014-05-04 19:45 UTC (permalink / raw) To: Peter Maydell; +Cc: QEMU Developers, Anthony Liguori On Sun, May 04, 2014 at 08:36:20PM +0100, Peter Maydell wrote: > OK, so you have a kernel (possibly just kernel config) problem > here -- this means QEMU got EPERM trying to open /dev/kvm. Yes for some reason it was 0600. I set it to 0666. > This isn't going to work for aarch64 at the moment because: > * KVM aarch64 currently requires '-cpu host' OK -- I will play with libguestfs to make sure it passes this flag, and try again. Currently waiting for the host (which has panicked again) to be rebooted manually. Thanks again, Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming and virtualization blog: http://rwmj.wordpress.com virt-df lists disk usage of guests without needing to install any software inside the virtual machine. Supports Linux and Windows. http://people.redhat.com/~rjones/virt-df/ ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-04 19:45 ` Richard W.M. Jones @ 2014-05-04 19:55 ` Peter Maydell 0 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2014-05-04 19:55 UTC (permalink / raw) To: Richard W.M. Jones; +Cc: QEMU Developers, Anthony Liguori On 4 May 2014 20:45, Richard W.M. Jones <rjones@redhat.com> wrote: > On Sun, May 04, 2014 at 08:36:20PM +0100, Peter Maydell wrote: >> OK, so you have a kernel (possibly just kernel config) problem >> here -- this means QEMU got EPERM trying to open /dev/kvm. > > Yes for some reason it was 0600. I set it to 0666. > >> This isn't going to work for aarch64 at the moment because: >> * KVM aarch64 currently requires '-cpu host' > > OK -- I will play with libguestfs to make sure it passes this flag, > and try again. It should in theory be possible to get -cpu cortex-a57 to work (though I haven't tried it so it's likely missing something trivial); however that will only work if your host CPU is actually a Cortex-A57. For any other host you'll need -cpu host. > Currently waiting for the host (which has panicked > again) to be rebooted manually. If your host has panicked that's a kernel bug :-) (or possibly a hardware bug if you're unlucky). If it does so reproducibly when you prod it with QEMU then you should probably retest with a recent kernel and report it to the kvm-arm mailing list. thanks -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2014-05-04 18:48 ` Peter Maydell 2014-05-04 18:58 ` Richard W.M. Jones @ 2014-05-04 19:29 ` Richard W.M. Jones 1 sibling, 0 replies; 32+ messages in thread From: Richard W.M. Jones @ 2014-05-04 19:29 UTC (permalink / raw) To: Peter Maydell; +Cc: QEMU Developers, Anthony Liguori I think this problem comes from my environment adding -fPIE. In any case, without that flag it doesn't crash in qemu (it kernel panics instead ..) Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming and virtualization blog: http://rwmj.wordpress.com libguestfs lets you edit virtual machines. Supports shell scripting, bindings from many languages. http://libguestfs.org ^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2015-03-11 14:18 Peter Maydell
2015-03-11 18:21 ` Peter Maydell
0 siblings, 1 reply; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
target-arm queue: mostly bug fixes, but also the Netduino 2
machine model. I'm letting that in (even though it's nearly
hardfreeze) since a new board model isn't going to impact
other existing uses, and the patches were posted well before
softfreeze deadline.
-- PMM
The following changes since commit 48412371415a260d00fc7fdcdb400da55f268828:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2015-03-11 11:12:35 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150311
for you to fetch changes up to 4f9950520a115acf9c0a209f0befa45758ad0215:
bitops.h: sextract64() return type should be int64_t, not uint64_t (2015-03-11 13:21:06 +0000)
----------------------------------------------------------------
target-arm queue:
* fix a bug in bitops.h
* implement SD card support on integratorcp
* add a missing 'compatible' property for Cortex-A57
* add Netduino 2 machine model
* fix command line parsing bug for CPU options with multiple CPUs
----------------------------------------------------------------
Alistair Francis (5):
stm32f2xx_timer: Add the stm32f2xx Timer
stm32f2xx_USART: Add the stm32f2xx USART Controller
stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG
stm32f205: Add the stm32f205 SoC
netduino2: Add the Netduino 2 Machine
Ard Biesheuvel (1):
hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1
Jan Kiszka (2):
integrator/cp: Model CP control registers as sysbus device
integrator/cp: Implement CARDIN and WPROT signals
Peter Maydell (1):
bitops.h: sextract64() return type should be int64_t, not uint64_t
Ryota Ozaki (1):
target-arm: Add missing compatible property to A57
default-configs/arm-softmmu.mak | 4 +
hw/arm/Makefile.objs | 2 +
hw/arm/integratorcp.c | 95 +++++++++--
hw/arm/netduino2.c | 57 +++++++
hw/arm/stm32f205_soc.c | 160 ++++++++++++++++++
hw/arm/virt.c | 4 +-
hw/char/Makefile.objs | 1 +
hw/char/stm32f2xx_usart.c | 229 ++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/stm32f2xx_syscfg.c | 160 ++++++++++++++++++
hw/timer/Makefile.objs | 2 +
hw/timer/stm32f2xx_timer.c | 328 +++++++++++++++++++++++++++++++++++++
include/hw/arm/stm32f205_soc.h | 57 +++++++
include/hw/char/stm32f2xx_usart.h | 73 +++++++++
include/hw/misc/stm32f2xx_syscfg.h | 61 +++++++
include/hw/timer/stm32f2xx_timer.h | 101 ++++++++++++
include/qemu/bitops.h | 2 +-
target-arm/cpu64.c | 1 +
18 files changed, 1323 insertions(+), 15 deletions(-)
create mode 100644 hw/arm/netduino2.c
create mode 100644 hw/arm/stm32f205_soc.c
create mode 100644 hw/char/stm32f2xx_usart.c
create mode 100644 hw/misc/stm32f2xx_syscfg.c
create mode 100644 hw/timer/stm32f2xx_timer.c
create mode 100644 include/hw/arm/stm32f205_soc.h
create mode 100644 include/hw/char/stm32f2xx_usart.h
create mode 100644 include/hw/misc/stm32f2xx_syscfg.h
create mode 100644 include/hw/timer/stm32f2xx_timer.h
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2015-03-11 14:18 Peter Maydell @ 2015-03-11 18:21 ` Peter Maydell 0 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2015-03-11 18:21 UTC (permalink / raw) To: QEMU Developers On 11 March 2015 at 14:18, Peter Maydell <peter.maydell@linaro.org> wrote: > target-arm queue: mostly bug fixes, but also the Netduino 2 > machine model. I'm letting that in (even though it's nearly > hardfreeze) since a new board model isn't going to impact > other existing uses, and the patches were posted well before > softfreeze deadline. Applied, thanks. PS: if you see "unknown device" failures in make check, this is a bug in our makefile/dependency generation stuff (currently being worked on). The workaround is to rm $BUILD_TREE/*/config-devices.mak -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2018-03-23 18:49 Peter Maydell
2018-03-23 21:45 ` no-reply
2018-03-25 15:04 ` Peter Maydell
0 siblings, 2 replies; 32+ messages in thread
From: Peter Maydell @ 2018-03-23 18:49 UTC (permalink / raw)
To: qemu-devel
Ten arm-related bug fixes for 2.12...
thanks
-- PMM
The following changes since commit 4c2c1015905fa1d616750dfe024b4c0b35875950:
Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20180323' into staging (2018-03-23 10:20:54 +0000)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180323
for you to fetch changes up to 548f514cf89dd9ab39c0cb4c063097bccf141fdd:
target/arm: Always set FAR to a known unknown value for debug exceptions (2018-03-23 18:26:46 +0000)
----------------------------------------------------------------
target-arm queue:
* arm/translate-a64: don't lose interrupts after unmasking via write to DAIF
* sdhci: fix incorrect use of Error *
* hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses
* hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15
* i.MX: Support serial RS-232 break properly
* mach-virt: Set VM's SMBIOS system version to mc->name
* target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK
* target/arm: Factor out code to calculate FSR for debug exceptions
* target/arm: Set FSR for BKPT, BRK when raising exception
* target/arm: Always set FAR to a known unknown value for debug exceptions
----------------------------------------------------------------
Paolo Bonzini (1):
sdhci: fix incorrect use of Error *
Peter Maydell (6):
hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses
hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15
target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK
target/arm: Factor out code to calculate FSR for debug exceptions
target/arm: Set FSR for BKPT, BRK when raising exception
target/arm: Always set FAR to a known unknown value for debug exceptions
Trent Piepho (1):
i.MX: Support serial RS-232 break properly
Victor Kamensky (1):
arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT
Wei Huang (1):
mach-virt: Set VM's SMBIOS system version to mc->name
include/hw/arm/virt.h | 1 +
include/hw/char/imx_serial.h | 1 +
target/arm/helper.h | 1 +
target/arm/internals.h | 25 +++++++++++++++++++++++++
hw/arm/bcm2836.c | 2 +-
hw/arm/raspi.c | 2 +-
hw/arm/virt.c | 8 +++++++-
hw/char/imx_serial.c | 5 ++++-
hw/intc/arm_gicv3_cpuif.c | 6 +++---
hw/sd/sdhci.c | 4 ++--
target/arm/helper.c | 1 -
target/arm/op_helper.c | 33 ++++++++++++++++++++++-----------
target/arm/translate-a64.c | 21 ++++++++++++++++-----
target/arm/translate.c | 19 ++++++++++++++-----
14 files changed, 98 insertions(+), 31 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2018-03-23 18:49 Peter Maydell @ 2018-03-23 21:45 ` no-reply 2018-03-25 15:04 ` Peter Maydell 1 sibling, 0 replies; 32+ messages in thread From: no-reply @ 2018-03-23 21:45 UTC (permalink / raw) To: peter.maydell; +Cc: famz, qemu-devel Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180323184958.14252-1-peter.maydell@linaro.org Subject: [Qemu-devel] [PULL 00/10] target-arm queue === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline $BASE.. | wc -l) failed=0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram commits="$(git log --format=%H --reverse $BASE..)" for c in $commits; do echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..." if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then failed=1 echo fi n=$((n+1)) done exit $failed === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' e4250a6575 target/arm: Always set FAR to a known unknown value for debug exceptions 5f8ad1e5dc target/arm: Set FSR for BKPT, BRK when raising exception 1f8698e782 target/arm: Factor out code to calculate FSR for debug exceptions 01c3c783a2 target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK 6fdd8ed47e mach-virt: Set VM's SMBIOS system version to mc->name 4c27421e3d i.MX: Support serial RS-232 break properly 541bf9ad10 hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15 4ba4d6edd9 hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses c5d1bc28c0 sdhci: fix incorrect use of Error * c8c419d13c arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT === OUTPUT BEGIN === Checking PATCH 1/10: arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT... Checking PATCH 2/10: sdhci: fix incorrect use of Error *... Checking PATCH 3/10: hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses... Checking PATCH 4/10: hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15... Checking PATCH 5/10: i.MX: Support serial RS-232 break properly... ERROR: spaces required around that '<<' (ctx:VxV) #56: FILE: include/hw/char/imx_serial.h:29: +#define URXD_FRMERR (1<<12) /* Character has frame error */ ^ total: 1 errors, 0 warnings, 24 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 6/10: mach-virt: Set VM's SMBIOS system version to mc->name... Checking PATCH 7/10: target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK... Checking PATCH 8/10: target/arm: Factor out code to calculate FSR for debug exceptions... Checking PATCH 9/10: target/arm: Set FSR for BKPT, BRK when raising exception... Checking PATCH 10/10: target/arm: Always set FAR to a known unknown value for debug exceptions... === OUTPUT END === Test command exited with code: 1 --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-devel@freelists.org ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2018-03-23 18:49 Peter Maydell 2018-03-23 21:45 ` no-reply @ 2018-03-25 15:04 ` Peter Maydell 1 sibling, 0 replies; 32+ messages in thread From: Peter Maydell @ 2018-03-25 15:04 UTC (permalink / raw) To: QEMU Developers On 23 March 2018 at 18:49, Peter Maydell <peter.maydell@linaro.org> wrote: > Ten arm-related bug fixes for 2.12... > > thanks > -- PMM > > The following changes since commit 4c2c1015905fa1d616750dfe024b4c0b35875950: > > Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20180323' into staging (2018-03-23 10:20:54 +0000) > > are available in the Git repository at: > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180323 > > for you to fetch changes up to 548f514cf89dd9ab39c0cb4c063097bccf141fdd: > > target/arm: Always set FAR to a known unknown value for debug exceptions (2018-03-23 18:26:46 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * arm/translate-a64: don't lose interrupts after unmasking via write to DAIF > * sdhci: fix incorrect use of Error * > * hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses > * hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15 > * i.MX: Support serial RS-232 break properly > * mach-virt: Set VM's SMBIOS system version to mc->name > * target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK > * target/arm: Factor out code to calculate FSR for debug exceptions > * target/arm: Set FSR for BKPT, BRK when raising exception > * target/arm: Always set FAR to a known unknown value for debug exceptions > Applied, thanks. -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2018-11-19 15:57 Peter Maydell
2018-11-19 18:10 ` Peter Maydell
0 siblings, 1 reply; 32+ messages in thread
From: Peter Maydell @ 2018-11-19 15:57 UTC (permalink / raw)
To: qemu-devel
Some Arm bugfixes for rc2...
thanks
-- PMM
The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119
for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:
MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)
----------------------------------------------------------------
target-arm queue:
* various MAINTAINERS file updates
* hw/block/onenand: use qemu_log_mask() for reporting
* hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
on the n800 and n810 machine models
* target/arm: fix smc incorrectly trapping to EL3 when secure is off
* hw/arm/stm32f205: Fix the UART and Timer region size
* target/arm: read ID registers for KVM guests so they can be
used to gate "is feature X present" checks
----------------------------------------------------------------
Luc Michel (1):
target/arm: fix smc incorrectly trapping to EL3 when secure is off
Peter Maydell (3):
hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
hw/block/onenand: use qemu_log_mask() for reporting
MAINTAINERS: list myself as maintainer for various Arm boards
Richard Henderson (4):
target/arm: Install ARMISARegisters from kvm host
target/arm: Fill in ARMISARegisters for kvm64
target/arm: Introduce read_sys_reg32 for kvm32
target/arm: Fill in ARMISARegisters for kvm32
Seth Kintigh (1):
hw/arm/stm32f205: Fix the UART and Timer region size
Thomas Huth (1):
MAINTAINERS: Add entries for missing ARM boards
target/arm/kvm_arm.h | 1 +
hw/block/onenand.c | 24 +++++-----
hw/char/stm32f2xx_usart.c | 2 +-
hw/timer/stm32f2xx_timer.c | 2 +-
target/arm/kvm.c | 1 +
target/arm/kvm32.c | 77 ++++++++++++++++++++------------
target/arm/kvm64.c | 90 +++++++++++++++++++++++++++++++++++++-
target/arm/op_helper.c | 54 +++++++++++++++++++----
MAINTAINERS | 106 +++++++++++++++++++++++++++++++++++++++------
9 files changed, 293 insertions(+), 64 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2018-11-19 15:57 Peter Maydell @ 2018-11-19 18:10 ` Peter Maydell 0 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2018-11-19 18:10 UTC (permalink / raw) To: QEMU Developers On 19 November 2018 at 15:57, Peter Maydell <peter.maydell@linaro.org> wrote: > Some Arm bugfixes for rc2... > > thanks > -- PMM > > The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812: > > Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119 > > for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e: > > MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * various MAINTAINERS file updates > * hw/block/onenand: use qemu_log_mask() for reporting > * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read > on the n800 and n810 machine models > * target/arm: fix smc incorrectly trapping to EL3 when secure is off > * hw/arm/stm32f205: Fix the UART and Timer region size > * target/arm: read ID registers for KVM guests so they can be > used to gate "is feature X present" checks > > ---------------------------------------------------------------- Applied, thanks. -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2019-07-15 13:42 Peter Maydell
2019-07-15 14:18 ` Peter Maydell
` (2 more replies)
0 siblings, 3 replies; 32+ messages in thread
From: Peter Maydell @ 2019-07-15 13:42 UTC (permalink / raw)
To: qemu-devel
target-arm queue for rc1 -- these are all bug fixes.
thanks
-- PMM
The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715
for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:
target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)
----------------------------------------------------------------
target-arm queue:
* report ARMv8-A FP support for AArch32 -cpu max
* hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
* hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
* hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
* hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
* hw/arm/virt: Fix non-secure flash mode
* pl031: Correctly migrate state when using -rtc clock=host
* fix regression that meant arm926 and arm1026 lost VFP
double-precision support
* v8M: NS BusFault on vector table fetch escalates to NS HardFault
----------------------------------------------------------------
Alex Bennée (1):
target/arm: report ARMv8-A FP support for AArch32 -cpu max
David Engraf (1):
hw/arm/virt: Fix non-secure flash mode
Peter Maydell (3):
pl031: Correctly migrate state when using -rtc clock=host
target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
target/arm: NS BusFault on vector table fetch escalates to NS HardFault
Philippe Mathieu-Daudé (5):
hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
include/hw/timer/pl031.h | 2 ++
hw/arm/virt.c | 2 +-
hw/core/machine.c | 1 +
hw/display/xlnx_dp.c | 15 +++++---
hw/ssi/mss-spi.c | 8 ++++-
hw/ssi/xilinx_spips.c | 43 +++++++++++++++-------
hw/timer/pl031.c | 92 +++++++++++++++++++++++++++++++++++++++++++++---
target/arm/cpu.c | 16 +++++++++
target/arm/m_helper.c | 21 ++++++++---
9 files changed, 174 insertions(+), 26 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2019-07-15 13:42 Peter Maydell @ 2019-07-15 14:18 ` Peter Maydell 2019-07-15 17:03 ` no-reply 2019-07-16 8:55 ` no-reply 2 siblings, 0 replies; 32+ messages in thread From: Peter Maydell @ 2019-07-15 14:18 UTC (permalink / raw) To: QEMU Developers On Mon, 15 Jul 2019 at 14:42, Peter Maydell <peter.maydell@linaro.org> wrote: > > target-arm queue for rc1 -- these are all bug fixes. > > thanks > -- PMM > > The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2: > > Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715 > > for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19: > > target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * report ARMv8-A FP support for AArch32 -cpu max > * hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory > * hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[] > * hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO > * hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO > * hw/arm/virt: Fix non-secure flash mode > * pl031: Correctly migrate state when using -rtc clock=host > * fix regression that meant arm926 and arm1026 lost VFP > double-precision support > * v8M: NS BusFault on vector table fetch escalates to NS HardFault > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2019-07-15 13:42 Peter Maydell 2019-07-15 14:18 ` Peter Maydell @ 2019-07-15 17:03 ` no-reply 2019-07-16 8:55 ` no-reply 2 siblings, 0 replies; 32+ messages in thread From: no-reply @ 2019-07-15 17:03 UTC (permalink / raw) To: peter.maydell; +Cc: qemu-devel Patchew URL: https://patchew.org/QEMU/20190715134211.23063-1-peter.maydell@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20190715134211.23063-1-peter.maydell@linaro.org Type: series Subject: [Qemu-devel] [PULL 00/10] target-arm queue === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === From https://github.com/patchew-project/qemu * [new tag] patchew/20190715134211.23063-1-peter.maydell@linaro.org -> patchew/20190715134211.23063-1-peter.maydell@linaro.org Switched to a new branch 'test' 374fdb936e target/arm: NS BusFault on vector table fetch escalates to NS HardFault a30b1dad81 target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026 6d7051773f pl031: Correctly migrate state when using -rtc clock=host 93d58455ba hw/arm/virt: Fix non-secure flash mode 08594d9831 hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO d4bfee6403 hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO 521dcfc621 hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[] 28dc994a87 hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory 33d10d39bd hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs 4ad540cb00 target/arm: report ARMv8-A FP support for AArch32 -cpu max === OUTPUT BEGIN === 1/10 Checking commit 4ad540cb003f (target/arm: report ARMv8-A FP support for AArch32 -cpu max) 2/10 Checking commit 33d10d39bd1e (hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs) 3/10 Checking commit 28dc994a8771 (hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory) 4/10 Checking commit 521dcfc62131 (hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]) 5/10 Checking commit d4bfee6403a6 (hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO) 6/10 Checking commit 08594d9831b4 (hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO) 7/10 Checking commit 93d58455baf6 (hw/arm/virt: Fix non-secure flash mode) 8/10 Checking commit 6d7051773f27 (pl031: Correctly migrate state when using -rtc clock=host) ERROR: spaces required around that '*' (ctx:VxV) #158: FILE: hw/timer/pl031.c:300: + .subsections = (const VMStateDescription*[]) { ^ total: 1 errors, 0 warnings, 146 lines checked Patch 8/10 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 9/10 Checking commit a30b1dad815c (target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026) 10/10 Checking commit 374fdb936ee9 (target/arm: NS BusFault on vector table fetch escalates to NS HardFault) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190715134211.23063-1-peter.maydell@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue 2019-07-15 13:42 Peter Maydell 2019-07-15 14:18 ` Peter Maydell 2019-07-15 17:03 ` no-reply @ 2019-07-16 8:55 ` no-reply 2 siblings, 0 replies; 32+ messages in thread From: no-reply @ 2019-07-16 8:55 UTC (permalink / raw) To: peter.maydell; +Cc: qemu-devel Patchew URL: https://patchew.org/QEMU/20190715134211.23063-1-peter.maydell@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PULL 00/10] target-arm queue Message-id: 20190715134211.23063-1-peter.maydell@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === From https://github.com/patchew-project/qemu * [new tag] patchew/20190715134211.23063-1-peter.maydell@linaro.org -> patchew/20190715134211.23063-1-peter.maydell@linaro.org Switched to a new branch 'test' 374fdb9 target/arm: NS BusFault on vector table fetch escalates to NS HardFault a30b1da target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026 6d70517 pl031: Correctly migrate state when using -rtc clock=host 93d5845 hw/arm/virt: Fix non-secure flash mode 08594d9 hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO d4bfee6 hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO 521dcfc hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[] 28dc994 hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory 33d10d3 hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs 4ad540c target/arm: report ARMv8-A FP support for AArch32 -cpu max === OUTPUT BEGIN === 1/10 Checking commit 4ad540cb003f (target/arm: report ARMv8-A FP support for AArch32 -cpu max) 2/10 Checking commit 33d10d39bd1e (hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs) 3/10 Checking commit 28dc994a8771 (hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory) 4/10 Checking commit 521dcfc62131 (hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]) 5/10 Checking commit d4bfee6403a6 (hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO) 6/10 Checking commit 08594d9831b4 (hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO) 7/10 Checking commit 93d58455baf6 (hw/arm/virt: Fix non-secure flash mode) 8/10 Checking commit 6d7051773f27 (pl031: Correctly migrate state when using -rtc clock=host) ERROR: spaces required around that '*' (ctx:VxV) #158: FILE: hw/timer/pl031.c:300: + .subsections = (const VMStateDescription*[]) { ^ total: 1 errors, 0 warnings, 146 lines checked Patch 8/10 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 9/10 Checking commit a30b1dad815c (target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026) 10/10 Checking commit 374fdb936ee9 (target/arm: NS BusFault on vector table fetch escalates to NS HardFault) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190715134211.23063-1-peter.maydell@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com ^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2019-07-16 8:56 UTC | newest] Thread overview: 32+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-12-13 18:30 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 01/10] arm: Fix CP15 FSR (C5) domain setting Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 02/10] target-arm: Infer ARMv4T feature from ARMv5 Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 03/10] target-arm: Infer ARMv5 feature from ARMv6 Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 04/10] target-arm: Infer ARMv6 feature from v6K Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 05/10] target-arm: Infer ARMv6(K) feature from ARMv7 Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 06/10] target-arm: Infer AUXCR feature from ARMv6 Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 07/10] target-arm: Infer Thumb2 feature from ARMv7 Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 08/10] target-arm: Infer Thumb division feature from M profile Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 09/10] target-arm: Infer VFP feature from VFPv3 Peter Maydell 2011-12-13 18:30 ` [Qemu-devel] [PATCH 10/10] target-arm: Infer VFPv3 feature from VFPv4 Peter Maydell 2011-12-14 20:41 ` [Qemu-devel] [PULL 00/10] target-arm queue andrzej zaborowski -- strict thread matches above, loose matches on Subject: below -- 2014-05-01 14:54 Peter Maydell 2014-05-02 11:11 ` Peter Maydell 2014-05-04 18:30 ` Richard W.M. Jones 2014-05-04 18:48 ` Peter Maydell 2014-05-04 18:58 ` Richard W.M. Jones 2014-05-04 19:36 ` Peter Maydell 2014-05-04 19:45 ` Richard W.M. Jones 2014-05-04 19:55 ` Peter Maydell 2014-05-04 19:29 ` Richard W.M. Jones 2015-03-11 14:18 Peter Maydell 2015-03-11 18:21 ` Peter Maydell 2018-03-23 18:49 Peter Maydell 2018-03-23 21:45 ` no-reply 2018-03-25 15:04 ` Peter Maydell 2018-11-19 15:57 Peter Maydell 2018-11-19 18:10 ` Peter Maydell 2019-07-15 13:42 Peter Maydell 2019-07-15 14:18 ` Peter Maydell 2019-07-15 17:03 ` no-reply 2019-07-16 8:55 ` no-reply
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