From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 1/3] target-mips: Streamline indexed cp1 memory addressing.
Date: Sat, 17 Dec 2011 14:21:44 -0800 [thread overview]
Message-ID: <1324160506-25183-2-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1324160506-25183-1-git-send-email-rth@twiddle.net>
We've already eliminated both base and index being zero.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-mips/translate.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..b20a817 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7749,8 +7749,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
} else if (index == 0) {
gen_load_gpr(t0, base);
} else {
- gen_load_gpr(t0, index);
- gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
+ gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
--
1.7.7.4
next prev parent reply other threads:[~2011-12-17 22:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-17 22:21 [Qemu-devel] [PATCH 0/3] target-mips improvements Richard Henderson
2011-12-17 22:21 ` Richard Henderson [this message]
2011-12-17 22:21 ` [Qemu-devel] [PATCH 2/3] mips-linux-user: Always support rdhwr Richard Henderson
2011-12-17 22:21 ` [Qemu-devel] [PATCH 3/3] target-mips: Implement Loongson Multimedia Instructions Richard Henderson
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