From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35375) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rc2dg-0003ev-Nn for qemu-devel@nongnu.org; Sat, 17 Dec 2011 17:21:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rc2df-0000pR-BV for qemu-devel@nongnu.org; Sat, 17 Dec 2011 17:21:56 -0500 Received: from mail-iy0-f173.google.com ([209.85.210.173]:52826) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rc2df-0000p4-8V for qemu-devel@nongnu.org; Sat, 17 Dec 2011 17:21:55 -0500 Received: by mail-iy0-f173.google.com with SMTP id j37so7270149iag.4 for ; Sat, 17 Dec 2011 14:21:55 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Sat, 17 Dec 2011 14:21:44 -0800 Message-Id: <1324160506-25183-2-git-send-email-rth@twiddle.net> In-Reply-To: <1324160506-25183-1-git-send-email-rth@twiddle.net> References: <1324160506-25183-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 1/3] target-mips: Streamline indexed cp1 memory addressing. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno We've already eliminated both base and index being zero. Signed-off-by: Richard Henderson --- target-mips/translate.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index d5b1c76..b20a817 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -7749,8 +7749,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } else if (index == 0) { gen_load_gpr(t0, base); } else { - gen_load_gpr(t0, index); - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ -- 1.7.7.4