From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 2/3] mips-linux-user: Always support rdhwr.
Date: Sat, 17 Dec 2011 14:21:45 -0800 [thread overview]
Message-ID: <1324160506-25183-3-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1324160506-25183-1-git-send-email-rth@twiddle.net>
The kernel will emulate this instruction if it's not supported
natively. This insn is used for TLS, among other things, and
so is required by modern glibc.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-mips/translate.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b20a817..e2ee763 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8118,7 +8118,11 @@ gen_rdhwr (CPUState *env, DisasContext *ctx, int rt, int rd)
{
TCGv t0;
+#if !defined(CONFIG_USER_ONLY)
+ /* The Linux kernel will emulate rdhwr if it's not supported natively.
+ Therefore only check the ISA in system mode. */
check_insn(env, ctx, ISA_MIPS32R2);
+#endif
t0 = tcg_temp_new();
switch (rd) {
--
1.7.7.4
next prev parent reply other threads:[~2011-12-17 22:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-17 22:21 [Qemu-devel] [PATCH 0/3] target-mips improvements Richard Henderson
2011-12-17 22:21 ` [Qemu-devel] [PATCH 1/3] target-mips: Streamline indexed cp1 memory addressing Richard Henderson
2011-12-17 22:21 ` Richard Henderson [this message]
2011-12-17 22:21 ` [Qemu-devel] [PATCH 3/3] target-mips: Implement Loongson Multimedia Instructions Richard Henderson
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