From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rey1O-0004CH-Vl for qemu-devel@nongnu.org; Sun, 25 Dec 2011 19:02:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rey1M-0006us-CL for qemu-devel@nongnu.org; Sun, 25 Dec 2011 19:02:30 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:58342) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rey1L-0006uL-PH for qemu-devel@nongnu.org; Sun, 25 Dec 2011 19:02:27 -0500 From: Peter Maydell Date: Mon, 26 Dec 2011 00:02:18 +0000 Message-Id: <1324857738-7916-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH] tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org On ARM, in Thumb mode r7 is used for the framepointer; this meant that we would fail to compile in debug mode because we were using r7 for TCG_AREG0. Shift to r6 instead to avoid this clash. (Bug reported as LP:870990.) Signed-off-by: Peter Maydell --- I did an extremely rough-and-ready benchmark with using a highreg instead and it didn't seem to make any difference, so I've stuck with using a lowreg as we do at the moment. dyngen-exec.h | 2 +- tcg/arm/tcg-target.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/dyngen-exec.h b/dyngen-exec.h index 3544372..09be9ea 100644 --- a/dyngen-exec.h +++ b/dyngen-exec.h @@ -31,7 +31,7 @@ #elif defined(_ARCH_PPC) #define AREG0 "r27" #elif defined(__arm__) -#define AREG0 "r7" +#define AREG0 "r6" #elif defined(__hppa__) #define AREG0 "r17" #elif defined(__mips__) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 48586c3..0035b47 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -78,7 +78,7 @@ typedef enum { enum { /* Note: must be synced with dyngen-exec.h */ - TCG_AREG0 = TCG_REG_R7, + TCG_AREG0 = TCG_REG_R6, }; static inline void flush_icache_range(unsigned long start, unsigned long stop) -- 1.7.5.4