From: Mark Langsdorf <mark.langsdorf@calxeda.com>
To: qemu-devel@nongnu.org
Cc: kwolf@redhat.com, peter.maydell@linaro.org,
Mark Langsdorf <mark.langsdorf@calxeda.com>,
paul@codesourcery.com, rob.herring@calxeda.com
Subject: [Qemu-devel] [PATCH v3 3/9] arm: add dummy v7 cp15 config_base_register
Date: Tue, 27 Dec 2011 14:13:41 -0600 [thread overview]
Message-ID: <1325016827-11503-4-git-send-email-mark.langsdorf@calxeda.com> (raw)
In-Reply-To: <1325016827-11503-1-git-send-email-mark.langsdorf@calxeda.com>
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
---
Changes from v2
Added test against op2
hanges from v1
renamed the register
added comments about how it will change when QOM CPUs are added
target-arm/cpu.h | 1 +
target-arm/helper.c | 14 ++++++++++++++
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c4d742f..449e620 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -149,6 +149,7 @@ typedef struct CPUARMState {
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
uint32_t c15_threadid; /* TI debugger thread-ID. */
+ uint32_t c15_config_base_address; /* SCU base address. */
} cp15;
struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..b235fed 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
* 0x200 << ($rn & 0xfff), when MMU is off. */
goto bad_reg;
}
+ if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
+ switch (crm) {
+ case 0:
+ /* The config_base_address should hold the value of
+ * the peripheral base. ARM should get this from a CPU
+ * object property, but that support isn't available in
+ * December 2011. Default to 0 for now and board models
+ * that care can set it by a private hook */
+ if ((op1 == 4) && (op2 == 0)) {
+ return env->cp15.c15_config_base_address;
+ }
+ }
+ goto bad_reg;
+ }
return 0;
}
bad_reg:
--
1.7.5.4
next prev parent reply other threads:[~2011-12-27 20:13 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-27 20:13 [Qemu-devel] [PATCH v3 0/9] various arm fixes Mark Langsdorf
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 1/9] arm: add missing scu registers Mark Langsdorf
2011-12-27 22:00 ` Peter Maydell
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 2/9] arm: Set frequencies for arm_timer Mark Langsdorf
2011-12-27 22:02 ` Peter Maydell
2011-12-27 20:13 ` Mark Langsdorf [this message]
2011-12-27 22:05 ` [Qemu-devel] [PATCH v3 3/9] arm: add dummy v7 cp15 config_base_register Peter Maydell
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 4/9] arm: add dummy gic security registers Mark Langsdorf
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 5/9] ahci: convert ahci_reset to use AHCIState Mark Langsdorf
2011-12-27 22:54 ` Peter Maydell
2011-12-27 23:20 ` Mark Langsdorf
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 6/9] ahci: add support for non-PCI based controllers Mark Langsdorf
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 7/9] add L2x0/PL310 cache controller device Mark Langsdorf
2011-12-28 0:23 ` Peter Maydell
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 8/9] Add xgmac ethernet model Mark Langsdorf
2011-12-28 0:39 ` Peter Maydell
2011-12-27 20:13 ` [Qemu-devel] [PATCH v3 9/9] arm: make number of a9mpcore GIC interrupts configurable Mark Langsdorf
2011-12-27 21:59 ` Peter Maydell
2011-12-27 22:04 ` Mark Langsdorf
2011-12-27 22:09 ` Peter Maydell
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