From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, afaerber@suse.de,
Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 3/4] target-mips: Add accessors for the two 32-bit halves of a 64-bit FPR
Date: Sat, 31 Dec 2011 15:54:50 +1100 [thread overview]
Message-ID: <1325307291-6334-3-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1325307291-6334-1-git-send-email-rth@twiddle.net>
Not much used yet, but more users to come.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-mips/translate.c | 46 ++++++++++++++++++++++++++++++----------------
1 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b6a7aeb..8908c8c 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -751,6 +751,29 @@ static void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
}
}
+static void gen_load_fpr_pair(DisasContext *ctx, TCGv_i32 tl,
+ TCGv_i32 th, int reg)
+{
+ gen_load_fpr32 (ctx, tl, reg);
+ gen_load_fpr32h (ctx, th, reg);
+}
+
+static void gen_store_fpr_pair(DisasContext *ctx, TCGv_i32 tl,
+ TCGv_i32 th, int reg)
+{
+#if TCG_TARGET_REG_BITS == 32
+ tcg_gen_mov_i32(TCGV_LOW(fpu_f64[reg]), tl);
+ tcg_gen_mov_i32(TCGV_HIGH(fpu_f64[reg]), th);
+#else
+ if (ctx->hflags & MIPS_HFLAG_F64) {
+ tcg_gen_concat32_i64(fpu_f64[reg], tl, th);
+ } else {
+ tcg_gen_mov_i32(fpu_f32[reg], tl);
+ tcg_gen_mov_i32(fpu_fh32[reg], th);
+ }
+#endif
+}
+
static inline int get_fp_bit (int cc)
{
if (cc)
@@ -7687,8 +7710,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_store_fpr32h(ctx, fp0, fd);
- gen_store_fpr32(ctx, fp1, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7702,8 +7724,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32h(ctx, fp1, ft);
- gen_store_fpr32(ctx, fp1, fd);
- gen_store_fpr32h(ctx, fp0, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7717,8 +7738,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32h(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_store_fpr32(ctx, fp1, fd);
- gen_store_fpr32h(ctx, fp0, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7732,8 +7752,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32h(ctx, fp0, fs);
gen_load_fpr32h(ctx, fp1, ft);
- gen_store_fpr32(ctx, fp1, fd);
- gen_store_fpr32h(ctx, fp0, fd);
+ gen_store_fpr_pair(ctx, fp1, fp0, fd);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
}
@@ -7905,10 +7924,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
tcg_gen_andi_tl(t0, t0, 0x7);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- gen_load_fpr32(ctx, fp, fs);
- gen_load_fpr32h(ctx, fph, fs);
- gen_store_fpr32(ctx, fp, fd);
- gen_store_fpr32h(ctx, fph, fd);
+ gen_load_fpr_pair(ctx, fp, fph, fs);
+ gen_store_fpr_pair(ctx, fp, fph, fd);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
@@ -7916,14 +7933,11 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
#ifdef TARGET_WORDS_BIGENDIAN
gen_load_fpr32(ctx, fp, fs);
gen_load_fpr32h(ctx, fph, ft);
- gen_store_fpr32h(ctx, fp, fd);
- gen_store_fpr32(ctx, fph, fd);
#else
gen_load_fpr32h(ctx, fph, fs);
gen_load_fpr32(ctx, fp, ft);
- gen_store_fpr32(ctx, fph, fd);
- gen_store_fpr32h(ctx, fp, fd);
#endif
+ gen_store_fpr_pair(ctx, fph, fp, fd);
gen_set_label(l2);
tcg_temp_free_i32(fp);
tcg_temp_free_i32(fph);
--
1.7.7.4
next prev parent reply other threads:[~2011-12-31 4:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-31 4:54 [Qemu-devel] [PATCH 1/4] target-mips: Pass DisasContext to fpr32 load/store routines Richard Henderson
2011-12-31 4:54 ` [Qemu-devel] [PATCH 2/4] target-mips: Use TCG registers for the FPU Richard Henderson
2011-12-31 4:54 ` Richard Henderson [this message]
2011-12-31 4:54 ` [Qemu-devel] [PATCH 4/4] target-mips: Fix MIPS_DEBUG Richard Henderson
2011-12-31 11:50 ` Peter Maydell
2011-12-31 22:23 ` Richard Henderson
2011-12-31 12:03 ` Andreas Färber
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