From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzU-0008Tc-Rg for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RgqzT-0000fb-H5 for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:20 -0500 Received: from mail-gx0-f173.google.com ([209.85.161.173]:45215) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzT-0000f5-Cr for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:19 -0500 Received: by mail-gx0-f173.google.com with SMTP id k1so10741955ggn.4 for ; Fri, 30 Dec 2011 20:56:19 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Sat, 31 Dec 2011 15:54:50 +1100 Message-Id: <1325307291-6334-3-git-send-email-rth@twiddle.net> In-Reply-To: <1325307291-6334-1-git-send-email-rth@twiddle.net> References: <1325307291-6334-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 3/4] target-mips: Add accessors for the two 32-bit halves of a 64-bit FPR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, afaerber@suse.de, Aurelien Jarno Not much used yet, but more users to come. Signed-off-by: Richard Henderson --- target-mips/translate.c | 46 ++++++++++++++++++++++++++++++---------------- 1 files changed, 30 insertions(+), 16 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index b6a7aeb..8908c8c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -751,6 +751,29 @@ static void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) } } +static void gen_load_fpr_pair(DisasContext *ctx, TCGv_i32 tl, + TCGv_i32 th, int reg) +{ + gen_load_fpr32 (ctx, tl, reg); + gen_load_fpr32h (ctx, th, reg); +} + +static void gen_store_fpr_pair(DisasContext *ctx, TCGv_i32 tl, + TCGv_i32 th, int reg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(TCGV_LOW(fpu_f64[reg]), tl); + tcg_gen_mov_i32(TCGV_HIGH(fpu_f64[reg]), th); +#else + if (ctx->hflags & MIPS_HFLAG_F64) { + tcg_gen_concat32_i64(fpu_f64[reg], tl, th); + } else { + tcg_gen_mov_i32(fpu_f32[reg], tl); + tcg_gen_mov_i32(fpu_fh32[reg], th); + } +#endif +} + static inline int get_fp_bit (int cc) { if (cc) @@ -7687,8 +7710,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_store_fpr32h(ctx, fp0, fd); - gen_store_fpr32(ctx, fp1, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7702,8 +7724,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32h(ctx, fp1, ft); - gen_store_fpr32(ctx, fp1, fd); - gen_store_fpr32h(ctx, fp0, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7717,8 +7738,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32h(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_store_fpr32(ctx, fp1, fd); - gen_store_fpr32h(ctx, fp0, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7732,8 +7752,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32h(ctx, fp0, fs); gen_load_fpr32h(ctx, fp1, ft); - gen_store_fpr32(ctx, fp1, fd); - gen_store_fpr32h(ctx, fp0, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7905,10 +7924,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(t0, t0, 0x7); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); - gen_load_fpr32(ctx, fp, fs); - gen_load_fpr32h(ctx, fph, fs); - gen_store_fpr32(ctx, fp, fd); - gen_store_fpr32h(ctx, fph, fd); + gen_load_fpr_pair(ctx, fp, fph, fs); + gen_store_fpr_pair(ctx, fp, fph, fd); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); @@ -7916,14 +7933,11 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, #ifdef TARGET_WORDS_BIGENDIAN gen_load_fpr32(ctx, fp, fs); gen_load_fpr32h(ctx, fph, ft); - gen_store_fpr32h(ctx, fp, fd); - gen_store_fpr32(ctx, fph, fd); #else gen_load_fpr32h(ctx, fph, fs); gen_load_fpr32(ctx, fp, ft); - gen_store_fpr32(ctx, fph, fd); - gen_store_fpr32h(ctx, fp, fd); #endif + gen_store_fpr_pair(ctx, fph, fp, fd); gen_set_label(l2); tcg_temp_free_i32(fp); tcg_temp_free_i32(fph); -- 1.7.7.4