[Qemu-devel] [PATCH 0/3] PPC: Fix bamboo part 2

[Qemu-devel] [PATCH 0/3] PPC: Fix bamboo part 2

[Alexander Graf]

These patches work on top of the other patch set I sent out earlier. With these
patches I can successfully run user space code with -M bamboo.

Alex

Alexander Graf (3):
  PPC: Bamboo: recompile device tree
  PPC: 440: Default to 440EP CPU
  PPC: Enable 440EP CPU target

 hw/ppc440.c                 |    2 +-
 pc-bios/bamboo.dtb          |  Bin 3179 -> 3211 bytes
 pc-bios/bamboo.dts          |  128 ++++++++++++++++---------------------------
 target-ppc/translate_init.c |   16 ++----
 4 files changed, 53 insertions(+), 93 deletions(-)

[Qemu-devel] [PATCH 1/3] PPC: Bamboo: recompile device tree

[Alexander Graf]

Recent dtc doesn't compile our dts anymore. Change all hex numbers to have
0x prefixes, indicate the old version and recompile using recent dtc.

This doesn't change any semantics in the device tree.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 pc-bios/bamboo.dtb |  Bin 3179 -> 3211 bytes
 pc-bios/bamboo.dts |  128 +++++++++++++++++++---------------------------------
 2 files changed, 47 insertions(+), 81 deletions(-)

diff --git a/pc-bios/bamboo.dtb b/pc-bios/bamboo.dtb
index c78e2544c0d7b22b49cb7d042100e8cbb0d30af8..d12e201aa0d855e5e2423b17976fb797177c00e5 100644
GIT binary patch
delta 92
zcmaDY(JiTQf%o5A1_qvP1_lNT1_rJdKw1Nc1%X%qh=G7{F;INN<cplb8?DbUaxw#j
eSb+HcB&Od8&gL&n!mNyZlO5RPH>-2FumAvhtP+?2

delta 73
zcmeB{d@Z4If%o5A1_qvN1_lNT1_rJZKw1Nc1%X)L-`jof85kHB1H~sy{>Ul3(fSPI
ZWO1f1o28j~SQ$koC$PzHcIR+m0RY<J6N&%;

diff --git a/pc-bios/bamboo.dts b/pc-bios/bamboo.dts
index 655442c..62fabcc 100644
--- a/pc-bios/bamboo.dts
+++ b/pc-bios/bamboo.dts
@@ -9,12 +9,14 @@
  * any warranty of any kind, whether express or implied.
  */
 
+/dts-v1/;
+
 / {
 	#address-cells = <2>;
 	#size-cells = <1>;
 	model = "amcc,bamboo";
 	compatible = "amcc,bamboo";
-	dcr-parent = <&/cpus/cpu@0>;
+	dcr-parent = <&{/cpus/cpu@0}>;
 
 	aliases {
 		serial0 = &UART0;
@@ -29,12 +31,12 @@
 			device_type = "cpu";
 			model = "PowerPC,440EP";
 			reg = <0>;
-			clock-frequency = <1fca0550>;
-			timebase-frequency = <017d7840>;
-			i-cache-line-size = <20>;
-			d-cache-line-size = <20>;
-			i-cache-size = <8000>;
-			d-cache-size = <8000>;
+			clock-frequency = <0x1fca0550>;
+			timebase-frequency = <0x017d7840>;
+			i-cache-line-size = <0x20>;
+			d-cache-line-size = <0x20>;
+			i-cache-size = <0x8000>;
+			d-cache-size = <0x8000>;
 			dcr-controller;
 			dcr-access-method = "native";
 		};
@@ -42,40 +44,27 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0 0 9000000>;
+		reg = <0x0 0x0 0x9000000>;
 	};
 
 	UIC0: interrupt-controller0 {
 		compatible = "ibm,uic-440ep","ibm,uic";
 		interrupt-controller;
-		cell-index = <0>;
-		dcr-reg = <0c0 009>;
-		#address-cells = <0>;
-		#size-cells = <0>;
-		#interrupt-cells = <2>;
-	};
-/*
-	UIC1: interrupt-controller1 {
-		compatible = "ibm,uic-440ep","ibm,uic";
-		interrupt-controller;
-		cell-index = <1>;
-		dcr-reg = <0d0 009>;
-		#address-cells = <0>;
-		#size-cells = <0>;
-		#interrupt-cells = <2>;
-		interrupts = <1e 4 1f 4>;
-		interrupt-parent = <&UIC0>;
+		cell-index = <0x0>;
+		dcr-reg = <0x0c0 0x009>;
+		#address-cells = <0x0>;
+		#size-cells = <0x0>;
+		#interrupt-cells = <0x2>;
 	};
-*/
 
 	SDR0: sdr {
 		compatible = "ibm,sdr-440ep";
-		dcr-reg = <00e 002>;
+		dcr-reg = <0x00e 0x002>;
 	};
 
 	CPR0: cpr {
 		compatible = "ibm,cpr-440ep";
-		dcr-reg = <00c 002>;
+		dcr-reg = <0x00c 0x002>;
 	};
 
 	plb {
@@ -83,16 +72,16 @@
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges;
-		clock-frequency = <07f28154>;
+		clock-frequency = <0x07f28154>;
 
 		SDRAM0: sdram {
 			compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
-			dcr-reg = <010 2>;
+			dcr-reg = <0x010 0x2>;
 		};
 
 		DMA0: dma {
 			compatible = "ibm,dma-440ep", "ibm,dma-440gp";
-			dcr-reg = <100 027>;
+			dcr-reg = <0x100 0x027>;
 		};
 
 		POB0: opb {
@@ -102,18 +91,18 @@
 			/* Bamboo is oddball in the 44x world and doesn't use the ERPN
 			 * bits.
 			 */
-			ranges = <00000000 0 00000000 80000000
-			          80000000 0 80000000 80000000>;
+			ranges = <0x00000000 0x0 0x00000000 0x80000000
+			          0x80000000 0x0 0x80000000 0x80000000>;
 			/* interrupt-parent = <&UIC1>; */
 			interrupts = <7 4>;
-			clock-frequency = <03f940aa>;
+			clock-frequency = <0x03f940aa>;
 
 			EBC0: ebc {
 				compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
-				dcr-reg = <012 2>;
+				dcr-reg = <0x012 2>;
 				#address-cells = <2>;
 				#size-cells = <1>;
-				clock-frequency = <03f940aa>;
+				clock-frequency = <0x03f940aa>;
 				interrupts = <5 1>;
 			/* interrupt-parent = <&UIC1>; */
 			};
@@ -121,10 +110,10 @@
 			UART0: serial@ef600300 {
 				device_type = "serial";
 				compatible = "ns16550";
-				reg = <ef600300 8>;
-				virtual-reg = <ef600300>;
-				clock-frequency = <00a8c000>;
-				current-speed = <1c200>;
+				reg = <0xef600300 8>;
+				virtual-reg = <0xef600300>;
+				clock-frequency = <0x00a8c000>;
+				current-speed = <0x1c200>;
 				interrupt-parent = <&UIC0>;
 				interrupts = <0 4>;
 			};
@@ -132,41 +121,18 @@
 			UART1: serial@ef600400 {
 				device_type = "serial";
 				compatible = "ns16550";
-				reg = <ef600400 8>;
-				virtual-reg = <ef600400>;
-				clock-frequency = <00a8c000>;
+				reg = <0xef600400 8>;
+				virtual-reg = <0xef600400>;
+				clock-frequency = <0x00a8c000>;
 				current-speed = <0>;
 				interrupt-parent = <&UIC0>;
 				interrupts = <1 4>;
 			};
-/*
-			UART2: serial@ef600500 {
-				device_type = "serial";
-				compatible = "ns16550";
-				reg = <ef600500 8>;
-				virtual-reg = <ef600500>;
-				clock-frequency = <0>;
-				current-speed = <0>;
-				interrupt-parent = <&UIC0>;
-				interrupts = <3 4>;
-			};
-
-			UART3: serial@ef600600 {
-				device_type = "serial";
-				compatible = "ns16550";
-				reg = <ef600600 8>;
-				virtual-reg = <ef600600>;
-				clock-frequency = <0>;
-				current-speed = <0>;
-				interrupt-parent = <&UIC0>;
-				interrupts = <4 4>;
-			};
 
-*/
 			IIC0: i2c@ef600700 {
 				device_type = "i2c";
 				compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
-				reg = <ef600700 14>;
+				reg = <0xef600700 0x14>;
 				interrupt-parent = <&UIC0>;
 				interrupts = <2 4>;
 			};
@@ -174,7 +140,7 @@
 			IIC1: i2c@ef600800 {
 				device_type = "i2c";
 				compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
-				reg = <ef600800 14>;
+				reg = <0xef600800 14>;
 				interrupt-parent = <&UIC0>;
 				interrupts = <7 4>;
 			};
@@ -182,7 +148,7 @@
 			ZMII0: emac-zmii@ef600d00 {
 				device_type = "zmii-interface";
 				compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
-				reg = <ef600d00 c>;
+				reg = <0xef600d00 0xc>;
 			};
 
 		};
@@ -194,35 +160,35 @@
 			#address-cells = <3>;
 			compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
 			primary;
-			reg = <0 eec00000 8     /* Config space access */
-			       0 eed00000 4     /* IACK */
-			       0 eed00000 4     /* Special cycle */
-			       0 ef400000 40>;  /* Internal registers */
+			reg = <0 0xeec00000 8     /* Config space access */
+			       0 0xeed00000 4     /* IACK */
+			       0 0xeed00000 4     /* Special cycle */
+			       0 0xef400000 0x40>;  /* Internal registers */
 
 			/* Outbound ranges, one memory and one IO,
 			 * later cannot be changed. Chip supports a second
 			 * IO range but we don't use it for now
 			 */
-			ranges = <02000000 0 a0000000 0 a0000000 0 20000000
-				  01000000 0 00000000 0 e8000000 0 00010000>;
+			ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
+				  0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>;
 
 			/* Inbound 2GB range starting at 0 */
-			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+			dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>;
 
 			/* Bamboo has all 4 IRQ pins tied together per slot */
-			interrupt-map-mask = <f800 0 0 0>;
+			interrupt-map-mask = <0xf800 0 0 0>;
 			interrupt-map = <
 				/* IDSEL 1 */
-				0800 0 0 0 &UIC0 1c 8
+				0x0800 0 0 0 &UIC0 0x1c 8
 
 				/* IDSEL 2 */
-				1000 0 0 0 &UIC0 1b 8
+				0x1000 0 0 0 &UIC0 0x1b 8
 
 				/* IDSEL 3 */
-				1800 0 0 0 &UIC0 1a 8
+				0x1800 0 0 0 &UIC0 0x1a 8
 
 				/* IDSEL 4 */
-				2000 0 0 0 &UIC0 19 8
+				0x2000 0 0 0 &UIC0 0x19 8
 			>;
 		};
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 2/3] PPC: 440: Default to 440EP CPU

[Alexander Graf]

Today we're exposing a Virtex 440 CPU to the guest despite the fact
that we're telling the guest that we're running on a 440EP one in the
device tree.

So let's better default to a real 440EP to make things synced again.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc440.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/ppc440.c b/hw/ppc440.c
index f7779bf..8920abb 100644
--- a/hw/ppc440.c
+++ b/hw/ppc440.c
@@ -48,7 +48,7 @@ CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size,
     qemu_irq *pci_irqs;
 
     if (cpu_model == NULL) {
-        cpu_model = "440-Xilinx"; // XXX: should be 440EP
+        cpu_model = "440EP";
     }
     env = cpu_init(cpu_model);
     if (!env) {
-- 
1.6.0.2

[Qemu-devel] [PATCH 3/3] PPC: Enable 440EP CPU target

[Alexander Graf]

Now that we have 440 TLB emulation, we can also support running the 440EP
CPU target in system emulation mode.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate_init.c |   16 +++++-----------
 1 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8a7233f..34c3d5f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3515,6 +3515,9 @@ static void init_proc_405 (CPUPPCState *env)
 
 /* PowerPC 440 EP                                                            */
 #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
+                              PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
+                              PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
+                              PPC_FLOAT_STFIWX |                              \
                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
                               PPC_CACHE | PPC_CACHE_ICBI |                    \
                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
@@ -3522,7 +3525,7 @@ static void init_proc_405 (CPUPPCState *env)
                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
                               PPC_440_SPEC)
 #define POWERPC_INSNS2_440EP (PPC_NONE)
-#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
+#define POWERPC_MSRM_440EP   (0x000000000006FF30ULL)
 #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
 #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
 #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
@@ -3531,7 +3534,6 @@ static void init_proc_405 (CPUPPCState *env)
                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 #define check_pow_440EP      check_pow_nocheck
 
-__attribute__ (( unused ))
 static void init_proc_440EP (CPUPPCState *env)
 {
     /* Time base */
@@ -3592,7 +3594,7 @@ static void init_proc_440EP (CPUPPCState *env)
     init_excp_BookE(env);
     env->dcache_line_size = 32;
     env->icache_line_size = 32;
-    /* XXX: TODO: allocate internal IRQ controller */
+    ppc40x_irq_init(env);
 
     SET_FIT_PERIOD(12, 16, 20, 24);
     SET_WDT_PERIOD(20, 24, 28, 32);
@@ -7826,22 +7828,14 @@ static const ppc_def_t ppc_defs[] = {
     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
 #endif
     /* PowerPC 440 microcontrolers                                           */
-#if defined(TODO_USER_ONLY)
     /* PowerPC 440 EP                                                        */
     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
-#endif
-#if defined(TODO_USER_ONLY)
     /* PowerPC 440 EPa                                                       */
     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
-#endif
-#if defined(TODO_USER_ONLY)
     /* PowerPC 440 EPb                                                       */
     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
-#endif
-#if defined(TODO_USER_ONLY)
     /* PowerPC 440 EPX                                                       */
     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
-#endif
 #if defined(TODO_USER_ONLY)
     /* PowerPC 440 GP                                                        */
     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
-- 
1.6.0.2