From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RiU5N-0004h4-M6 for qemu-devel@nongnu.org; Wed, 04 Jan 2012 11:53:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RiU5J-0002Ki-Co for qemu-devel@nongnu.org; Wed, 04 Jan 2012 11:53:09 -0500 Received: from smtp131.dfw.emailsrvr.com ([67.192.241.131]:46877) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RiU5J-0002Kd-6Q for qemu-devel@nongnu.org; Wed, 04 Jan 2012 11:53:05 -0500 From: Mark Langsdorf Date: Wed, 4 Jan 2012 10:53:09 -0600 Message-Id: <1325695989-4202-1-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH v6 1/1] arm: add dummy v7 cp15 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, afaerber@suse.de, Mark Langsdorf Add dummy register support for the cp15, CRn=c15 registers. config_base_register and power_control_register currently default to 0, but may have improved support after the QOM CPU patches are finished. Signed-off-by: Mark Langsdorf --- Changes from v5 Added handling for all c15 registers Changes from v3, v4 None Changes from v2 Added test against op2 Changes from v1 renamed the register added comments about how it will change when QOM CPUs are added target-arm/cpu.h | 2 ++ target-arm/helper.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c4d742f..f8fb558 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -149,6 +149,8 @@ typedef struct CPUARMState { uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ uint32_t c15_threadid; /* TI debugger thread-ID. */ + uint32_t c15_config_base_address; /* SCU base address. */ + uint32_t c15_power_control; /* power control */ } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 65f4fbf..f39bcf3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2111,6 +2111,36 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) * 0x200 << ($rn & 0xfff), when MMU is off. */ goto bad_reg; } + if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) { + switch (crm) { + case 0: + if ((op1 == 4) && (op2 == 0)) { + /* The config_base_address should hold the value of + * the peripheral base. ARM should get this from a CPU + * object property, but that support isn't available in + * December 2011. Default to 0 for now and board models + * that care can set it by a private hook */ + return env->cp15.c15_config_base_address; + } else if ((op1 == 0) && (op2 == 0)) { + /* power_control should be set to maximum latency. Again, + default to 0 and set by private hook */ + return env->cp15.c15_power_control; + } + break; + case 1: /* NEON Busy */ + return 0; + case 5: /* tlb lockdown */ + case 6: + case 7: + if ((op1 == 5) && (op2 == 2)) { + return 0; + } + break; + default: + break; + } + goto bad_reg; + } return 0; } bad_reg: -- 1.7.5.4