From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH for-10.1 02/10] target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)
Date: Fri, 18 Jul 2025 14:32:08 -0700 [thread overview]
Message-ID: <1325fc26-ecd2-413c-adee-7dcff7d0b102@linaro.org> (raw)
In-Reply-To: <20250718173032.2498900-3-peter.maydell@linaro.org>
On 7/18/25 10:30, Peter Maydell wrote:
> FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point
> (predicated) instructions, which are encoded via sz=0b00.
> Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM; these are all the insns
> in this group which do not change behaviour for AH=1.
>
> We will deal with BFMAX/BFMIN (which do have different AH=1
> behaviour) in a following commit.
>
> Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> target/arm/tcg/helper-sve.h | 10 ++++++++++
> target/arm/tcg/sve_helper.c | 5 +++++
> target/arm/tcg/translate-sve.c | 22 +++++++++++++++++-----
> 3 files changed, 32 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2025-07-18 22:07 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-18 17:30 [PATCH for-10.1 00/10] target/arm: Some SVE2p1 fixes Peter Maydell
2025-07-18 17:30 ` [PATCH for-10.1 01/10] target/arm: Add BFADD, BFSUB, BFMUL (unpredicated) Peter Maydell
2025-07-18 21:29 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 02/10] target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated) Peter Maydell
2025-07-18 21:32 ` Richard Henderson [this message]
2025-07-18 17:30 ` [PATCH for-10.1 03/10] target/arm: Add BFMIN, BFMAX (predicated) Peter Maydell
2025-07-18 21:34 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 04/10] target/arm: Add BFMUL (indexed) Peter Maydell
2025-07-18 21:38 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 05/10] target/arm: Add BFMLA, BFMLS (vectors) Peter Maydell
2025-07-18 21:40 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 06/10] target/arm: Add BFMLA, BFMLS (indexed) Peter Maydell
2025-07-18 21:42 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 07/10] target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV Peter Maydell
2025-07-18 21:43 ` Richard Henderson
2025-07-21 8:21 ` Philippe Mathieu-Daudé
2025-07-18 17:30 ` [PATCH for-10.1 08/10] target/arm: Don't nest H() macro calls in SVE DO_REDUCE Peter Maydell
2025-07-18 21:44 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 09/10] target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV Peter Maydell
2025-07-18 21:45 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 10/10] target/arm: Make LD1Q decode and trans fn agree about a->u Peter Maydell
2025-07-18 21:46 ` Richard Henderson
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