[Qemu-devel] [PATCH] target-arm: Fix errors in decode of M profile CPS

[Qemu-devel] [PATCH] target-arm: Fix errors in decode of M profile CPS

[Peter Maydell]

Fix errors in the decode of M profile CPS:
 * the decode of the I (affects PRIMASK) and F (affects FAULTMASK)
   bits was reversed
 * the FAULTMASK system register number is 19, not 17

This fixes an issue reported as LP:913925.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Note that we fixed the misnumbering of FAULTMASK on the msr
helper side in commit 8284582.

 target-arm/translate.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index f91553a..280bfca 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9710,15 +9710,15 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
                 break;
             if (IS_M(env)) {
                 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
-                /* PRIMASK */
+                /* FAULTMASK */
                 if (insn & 1) {
-                    addr = tcg_const_i32(16);
+                    addr = tcg_const_i32(19);
                     gen_helper_v7m_msr(cpu_env, addr, tmp);
                     tcg_temp_free_i32(addr);
                 }
-                /* FAULTMASK */
+                /* PRIMASK */
                 if (insn & 2) {
-                    addr = tcg_const_i32(17);
+                    addr = tcg_const_i32(16);
                     gen_helper_v7m_msr(cpu_env, addr, tmp);
                     tcg_temp_free_i32(addr);
                 }
-- 
1.7.5.4