From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:45975) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RkNfx-0003FY-TH for qemu-devel@nongnu.org; Mon, 09 Jan 2012 17:26:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RkNfw-0001hD-JG for qemu-devel@nongnu.org; Mon, 09 Jan 2012 17:26:45 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:51950) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RkNfw-0001ga-Cf for qemu-devel@nongnu.org; Mon, 09 Jan 2012 17:26:44 -0500 From: Peter Maydell Date: Mon, 9 Jan 2012 22:26:35 +0000 Message-Id: <1326147995-2561-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH] target-arm: Fix errors in decode of M profile CPS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17 This fixes an issue reported as LP:913925. Signed-off-by: Peter Maydell --- Note that we fixed the misnumbering of FAULTMASK on the msr helper side in commit 8284582. target-arm/translate.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index f91553a..280bfca 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9710,15 +9710,15 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) break; if (IS_M(env)) { tmp = tcg_const_i32((insn & (1 << 4)) != 0); - /* PRIMASK */ + /* FAULTMASK */ if (insn & 1) { - addr = tcg_const_i32(16); + addr = tcg_const_i32(19); gen_helper_v7m_msr(cpu_env, addr, tmp); tcg_temp_free_i32(addr); } - /* FAULTMASK */ + /* PRIMASK */ if (insn & 2) { - addr = tcg_const_i32(17); + addr = tcg_const_i32(16); gen_helper_v7m_msr(cpu_env, addr, tmp); tcg_temp_free_i32(addr); } -- 1.7.5.4