From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl04H-0007ok-J2 for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:26:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rl04C-00027Y-Jl for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:26:25 -0500 Received: from smtp181.dfw.emailsrvr.com ([67.192.241.181]:37378) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl04C-000279-By for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:26:20 -0500 From: Mark Langsdorf Date: Wed, 11 Jan 2012 09:26:08 -0600 Message-Id: <1326295570-10060-5-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: <1326295570-10060-1-git-send-email-mark.langsdorf@calxeda.com> References: <1326213943-878-1-git-send-email-mark.langsdorf@calxeda.com> <1326295570-10060-1-git-send-email-mark.langsdorf@calxeda.com> Subject: [Qemu-devel] [PATCH v8 4/6] arm: Add dummy support for co-processor 15's secure config register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Mark Langsdorf , i.mitsyanko@gmail.com, Rob Herring , edgar.iglesias@gmail.com, afaerber@suse.de From: Rob Herring Signed-off-by: Rob Herring Signed-off-by: Mark Langsdorf Reviewed-by: Peter Maydell --- Changes from v7 None Changes from v1, v2, v3, v4, v5, v6 Skipped target-arm/cpu.h | 3 ++- target-arm/helper.c | 9 +++++++++ target-arm/machine.c | 2 ++ 3 files changed, 13 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 26b4981..42c53a7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -116,6 +116,7 @@ typedef struct CPUARMState { uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t c1_scr; /* secure config register. */ uint32_t c2_base0; /* MMU translation table base 0. */ uint32_t c2_base1; /* MMU translation table base 1. */ uint32_t c2_control; /* MMU translation table base control. */ @@ -452,7 +453,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 5 +#define CPU_SAVE_VERSION 6 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/helper.c b/target-arm/helper.c index fa42c64..00458fc 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1440,6 +1440,11 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) } goto bad_reg; case 1: /* System configuration. */ + if (arm_feature(env, ARM_FEATURE_V7) + && op1 == 0 && crm == 1 && op2 == 0) { + env->cp15.c1_scr = val; + break; + } if (arm_feature(env, ARM_FEATURE_OMAPCP)) op2 = 0; switch (op2) { @@ -1908,6 +1913,10 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) goto bad_reg; } case 1: /* System configuration. */ + if (arm_feature(env, ARM_FEATURE_V7) + && op1 == 0 && crm == 1 && op2 == 0) { + return env->cp15.c1_scr; + } if (arm_feature(env, ARM_FEATURE_OMAPCP)) op2 = 0; switch (op2) { diff --git a/target-arm/machine.c b/target-arm/machine.c index 8984775..f66b8df 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -26,6 +26,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->cp15.c1_sys); qemu_put_be32(f, env->cp15.c1_coproc); qemu_put_be32(f, env->cp15.c1_xscaleauxcr); + qemu_put_be32(f, env->cp15.c1_scr); qemu_put_be32(f, env->cp15.c2_base0); qemu_put_be32(f, env->cp15.c2_base1); qemu_put_be32(f, env->cp15.c2_control); @@ -143,6 +144,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->cp15.c1_sys = qemu_get_be32(f); env->cp15.c1_coproc = qemu_get_be32(f); env->cp15.c1_xscaleauxcr = qemu_get_be32(f); + env->cp15.c1_scr = qemu_get_be32(f); env->cp15.c2_base0 = qemu_get_be32(f); env->cp15.c2_base1 = qemu_get_be32(f); env->cp15.c2_control = qemu_get_be32(f); -- 1.7.5.4