From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59538) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl04L-0007z4-Fy for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:26:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rl04D-00027l-J4 for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:26:29 -0500 Received: from smtp181.dfw.emailsrvr.com ([67.192.241.181]:37378) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl04D-000279-AY for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:26:21 -0500 From: Mark Langsdorf Date: Wed, 11 Jan 2012 09:26:10 -0600 Message-Id: <1326295570-10060-7-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: <1326295570-10060-1-git-send-email-mark.langsdorf@calxeda.com> References: <1326213943-878-1-git-send-email-mark.langsdorf@calxeda.com> <1326295570-10060-1-git-send-email-mark.langsdorf@calxeda.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] =?utf-8?q?=5BPATCH_v8_6/6=5D_arm=3A_Remove_incorrect?= =?utf-8?q?_comment_in_arm=5Ftimer?= List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: i.mitsyanko@gmail.com, peter.maydell@linaro.org, afaerber@suse.de, Mark Langsdorf , edgar.iglesias@gmail.com The current comment says that the arm_timers are restricted to between 32 KHz and 1 MHz, but sp804 TRM does not specify those limits. Signed-off-by: Mark Langsdorf Reviewed-by: Andreas F=C3=A4rber --- Changes from v7 None Changes from v2, v3, v4, v5, v6 Skipped Changes from v1 Clarified the commit message hw/arm_timer.c | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 60e1c63..15d493f 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -272,11 +272,8 @@ static int sp804_init(SysBusDevice *dev) =20 qi =3D qemu_allocate_irqs(sp804_set_irq, s, 2); sysbus_init_irq(dev, &s->irq); - /* The timers are configurable between 32kHz and 1MHz - * defaulting to 1MHz but overrideable as individual properties */ s->timer[0] =3D arm_timer_init(s->freq0); s->timer[1] =3D arm_timer_init(s->freq1); - s->timer[0]->irq =3D qi[0]; s->timer[1]->irq =3D qi[1]; memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); --=20 1.7.5.4