[Qemu-devel] [PULL 0/2] target-arm queue

[Qemu-devel] [PULL 0/2] target-arm queue

[Peter Maydell]

A small target-arm pullreq, but I want to get the SCR change
committed because the Calxeda patchset depends on it, and then
the Samsung patchset is going to need to be updated to sit on
top of that, as are some Cortex-A15 related changes I've been
working on.

The M profile patch only went on the list on Monday, so this
is slightly early, but it's a pretty trivial change and I
thought I'd rather get the pullreq sent out before the weekend
rather than after.

thanks
-- PMM

The following changes since commit 6b620ca3b052e622eef4379cfe37c5c3db5364c9:

  prepare for future GPLv2+ relicensing (2012-01-13 10:55:56 -0600)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Peter Maydell (1):
      target-arm: Fix errors in decode of M profile CPS

Rob Herring (1):
      arm: Add dummy support for co-processor 15's secure config register

 target-arm/cpu.h       |    3 ++-
 target-arm/helper.c    |    9 +++++++++
 target-arm/machine.c   |    2 ++
 target-arm/translate.c |    8 ++++----
 4 files changed, 17 insertions(+), 5 deletions(-)

[Qemu-devel] [PATCH 1/2] target-arm: Fix errors in decode of M profile CPS

[Peter Maydell]

Fix errors in the decode of M profile CPS:
 * the decode of the I (affects PRIMASK) and F (affects FAULTMASK)
   bits was reversed
 * the FAULTMASK system register number is 19, not 17

This fixes an issue reported as LP:913925.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index f91553a..280bfca 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9710,15 +9710,15 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
                 break;
             if (IS_M(env)) {
                 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
-                /* PRIMASK */
+                /* FAULTMASK */
                 if (insn & 1) {
-                    addr = tcg_const_i32(16);
+                    addr = tcg_const_i32(19);
                     gen_helper_v7m_msr(cpu_env, addr, tmp);
                     tcg_temp_free_i32(addr);
                 }
-                /* FAULTMASK */
+                /* PRIMASK */
                 if (insn & 2) {
-                    addr = tcg_const_i32(17);
+                    addr = tcg_const_i32(16);
                     gen_helper_v7m_msr(cpu_env, addr, tmp);
                     tcg_temp_free_i32(addr);
                 }
-- 
1.7.1

[Qemu-devel] [PATCH 2/2] arm: Add dummy support for co-processor 15's secure config register

[Peter Maydell]

From: Rob Herring <rob.herring@calxeda.com>

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h     |    3 ++-
 target-arm/helper.c  |    9 +++++++++
 target-arm/machine.c |    2 ++
 3 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 26b4981..42c53a7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -116,6 +116,7 @@ typedef struct CPUARMState {
         uint32_t c1_sys; /* System control register.  */
         uint32_t c1_coproc; /* Coprocessor access register.  */
         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
+        uint32_t c1_scr; /* secure config register.  */
         uint32_t c2_base0; /* MMU translation table base 0.  */
         uint32_t c2_base1; /* MMU translation table base 1.  */
         uint32_t c2_control; /* MMU translation table base control.  */
@@ -452,7 +453,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
 
-#define CPU_SAVE_VERSION 5
+#define CPU_SAVE_VERSION 6
 
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fa42c64..00458fc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1440,6 +1440,11 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
         }
         goto bad_reg;
     case 1: /* System configuration.  */
+        if (arm_feature(env, ARM_FEATURE_V7)
+                && op1 == 0 && crm == 1 && op2 == 0) {
+            env->cp15.c1_scr = val;
+            break;
+        }
         if (arm_feature(env, ARM_FEATURE_OMAPCP))
             op2 = 0;
         switch (op2) {
@@ -1908,6 +1913,10 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
             goto bad_reg;
         }
     case 1: /* System configuration.  */
+        if (arm_feature(env, ARM_FEATURE_V7)
+            && op1 == 0 && crm == 1 && op2 == 0) {
+            return env->cp15.c1_scr;
+        }
         if (arm_feature(env, ARM_FEATURE_OMAPCP))
             op2 = 0;
         switch (op2) {
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 8984775..f66b8df 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -26,6 +26,7 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_be32(f, env->cp15.c1_sys);
     qemu_put_be32(f, env->cp15.c1_coproc);
     qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
+    qemu_put_be32(f, env->cp15.c1_scr);
     qemu_put_be32(f, env->cp15.c2_base0);
     qemu_put_be32(f, env->cp15.c2_base1);
     qemu_put_be32(f, env->cp15.c2_control);
@@ -143,6 +144,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     env->cp15.c1_sys = qemu_get_be32(f);
     env->cp15.c1_coproc = qemu_get_be32(f);
     env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
+    env->cp15.c1_scr = qemu_get_be32(f);
     env->cp15.c2_base0 = qemu_get_be32(f);
     env->cp15.c2_base1 = qemu_get_be32(f);
     env->cp15.c2_control = qemu_get_be32(f);
-- 
1.7.1

Re: [Qemu-devel] [PULL 0/2] target-arm queue

[Aurelien Jarno]

On Fri, Jan 13, 2012 at 05:50:37PM +0000, Peter Maydell wrote:
> A small target-arm pullreq, but I want to get the SCR change
> committed because the Calxeda patchset depends on it, and then
> the Samsung patchset is going to need to be updated to sit on
> top of that, as are some Cortex-A15 related changes I've been
> working on.
> 
> The M profile patch only went on the list on Monday, so this
> is slightly early, but it's a pretty trivial change and I
> thought I'd rather get the pullreq sent out before the weekend
> rather than after.
> 
> thanks
> -- PMM
> 
> The following changes since commit 6b620ca3b052e622eef4379cfe37c5c3db5364c9:
> 
>   prepare for future GPLv2+ relicensing (2012-01-13 10:55:56 -0600)
> 
> are available in the git repository at:
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
> 
> Peter Maydell (1):
>       target-arm: Fix errors in decode of M profile CPS
> 
> Rob Herring (1):
>       arm: Add dummy support for co-processor 15's secure config register
> 
>  target-arm/cpu.h       |    3 ++-
>  target-arm/helper.c    |    9 +++++++++
>  target-arm/machine.c   |    2 ++
>  target-arm/translate.c |    8 ++++----
>  4 files changed, 17 insertions(+), 5 deletions(-)
> 

Thanks, pulled.


-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net