From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:36759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RloAq-0002Ca-Vd for qemu-devel@nongnu.org; Fri, 13 Jan 2012 15:56:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RloAp-00064w-HI for qemu-devel@nongnu.org; Fri, 13 Jan 2012 15:56:32 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:37081) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RloAp-00063s-6g for qemu-devel@nongnu.org; Fri, 13 Jan 2012 15:56:31 -0500 From: Peter Maydell Date: Fri, 13 Jan 2012 20:52:38 +0000 Message-Id: <1326487969-12462-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1326487969-12462-1-git-send-email-peter.maydell@linaro.org> References: <1326487969-12462-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 01/12] vexpress, realview: Add (dummy) L2 cache controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: android-virt@lists.cs.columbia.edu, patches@linaro.org Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model. Signed-off-by: Peter Maydell --- hw/realview.c | 2 ++ hw/vexpress.c | 1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/hw/realview.c b/hw/realview.c index d4191e9..e52babc 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -225,6 +225,8 @@ static void realview_init(ram_addr_t ram_size, for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } + sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000, + NULL); } else { uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ diff --git a/hw/vexpress.c b/hw/vexpress.c index 0f39d8d..613be65 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -180,6 +180,7 @@ static void vexpress_a9_init(ram_addr_t ram_size, /* 0x100ec000 TrustZone Address Space Controller */ /* 0x10200000 CoreSight debug APB */ /* 0x1e00a000 PL310 L2 Cache Controller */ + sysbus_create_varargs("l2x0", 0x1e00a000, NULL); /* CS0: NOR0 flash : 0x40000000 .. 0x44000000 */ /* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */ -- 1.7.1