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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Andreas Färber" <andreas.faerber@web.de>, patches@linaro.org
Subject: [Qemu-devel] [PATCH 1/3] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
Date: Mon, 16 Jan 2012 18:34:16 +0000	[thread overview]
Message-ID: <1326738858-19992-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1326738858-19992-1-git-send-email-peter.maydell@linaro.org>

In the helper routines for VCVT float-to-int conversions, add
an explicit cast rather than relying on the softfloat int32
type being exactly 32 bits wide (which it is not guaranteed to be).
Without this, if the softfloat type was 64 bits wide we would
get zero-extension of the 32 bit value from the ARM register
rather than sign-extension, since TCG i32 values are passed as
uint32_t.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00458fc..e968c9c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2786,7 +2786,7 @@ DO_VFP_cmp(d, float64)
     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
 { \
     float_status *fpst = fpstp; \
-    return sign##int32_to_##float##fsz(x, fpst); \
+    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
 }
 
 #define CONV_FTOI(name, fsz, sign, round) \
-- 
1.7.1

  reply	other threads:[~2012-01-16 18:34 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-01-16 18:34 [Qemu-devel] [PATCH 0/3] softfloat/arm: fix 'int32 is 32 bits' assumptions Peter Maydell
2012-01-16 18:34 ` Peter Maydell [this message]
2012-01-16 18:34 ` [Qemu-devel] [PATCH 2/3] softfloat: float*_to_int32_round_to_zero: don't assume int32 is 32 bits Peter Maydell
2012-01-16 18:34 ` [Qemu-devel] [PATCH 3/3] softfloat: roundAndPackInt{32, 64}: Don't " Peter Maydell

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