[Qemu-devel] [PATCH 0/3] softfloat/arm: fix 'int32 is 32 bits' assumptions

[Qemu-devel] [PATCH 0/3] softfloat/arm: fix 'int32 is 32 bits' assumptions

[Peter Maydell]

These patches fix some assumptions that are made by various bits
of code that the softfloat 'int32' and 'uint32' types are exactly
32 bits rather than at least 32 bits. I found these issues as part
of testing Andreas' recent softfloat type fixes patchset. What
I did was to take the first four patches from Andreas' set (the
fixes for type mixups) and then do a test run of my ARM VFP/Neon
tests with the following two sets of typedefs:

/* maximum-width versions */
typedef uint64_t flag;
typedef uint64_t uint8;
typedef int64_t int8;
typedef uint64_t uint16;
typedef int64_t int16;
typedef uint64_t uint32;
typedef int64_t int32;
typedef uint64_t uint64;
typedef int64_t int64;

/* minimum-width versions */
typedef uint8_t flag;
typedef uint8_t uint8;
typedef int8_t int8;
typedef uint16_t uint16;
typedef int16_t int16;
typedef uint32_t uint32;
typedef int32_t int32;
typedef uint64_t uint64;
typedef int64_t int64;

to flush out the two obvious possible problems: code which
assumes the type is larger than it might be, and code which
assumes the type is not as large as it might be. These test
runs revealed a few bugs, which this patchseries fixes.
These are basically all assumptions about the size of int32
in float-to-int or int-to-float code, and represent real rather
than theoretical problems with the switch to int_fast*_t
since on 64 bit hosts int_fast32_t is typically 64 bits.

NB: I think I've fairly solidly exercised the bits of softfloat
that ARM uses, but can't guarantee coverage of anything that's
only used by other targets or target-specific non-ARM code.

Andreas: these sit after your patches 1-4, so it might be
easiest if you just stick them in your patch series; like
your 1-4 they can be applied now as they make sense even without
the type conversion patches.


Peter Maydell (3):
  target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
  softfloat: float*_to_int32_round_to_zero: don't assume int32 is 32 bits
  softfloat: roundAndPackInt{32,64}: Don't assume int32 is 32 bits

 fpu/softfloat.c     |   12 ++++++------
 target-arm/helper.c |    2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

[Qemu-devel] [PATCH 1/3] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only

[Peter Maydell]

In the helper routines for VCVT float-to-int conversions, add
an explicit cast rather than relying on the softfloat int32
type being exactly 32 bits wide (which it is not guaranteed to be).
Without this, if the softfloat type was 64 bits wide we would
get zero-extension of the 32 bit value from the ARM register
rather than sign-extension, since TCG i32 values are passed as
uint32_t.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00458fc..e968c9c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2786,7 +2786,7 @@ DO_VFP_cmp(d, float64)
     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
 { \
     float_status *fpst = fpstp; \
-    return sign##int32_to_##float##fsz(x, fpst); \
+    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
 }
 
 #define CONV_FTOI(name, fsz, sign, round) \
-- 
1.7.1

[Qemu-devel] [PATCH 2/3] softfloat: float*_to_int32_round_to_zero: don't assume int32 is 32 bits

[Peter Maydell]

Code in the float64_to_int32_round_to_zero() function was assuming
that int32 would not be wider than 32 bits; this meant it might
not correctly detect the overflow case. We take the simple approach
of using int32_t. Also fix equivalent issues in the functions
for other float sizes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 fpu/softfloat.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 6dbcb1b..08db899 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1378,7 +1378,7 @@ int32 float32_to_int32_round_to_zero( float32 a STATUS_PARAM )
     flag aSign;
     int16 aExp, shiftCount;
     uint32_t aSig;
-    int32 z;
+    int32_t z;
     a = float32_squash_input_denormal(a STATUS_VAR);
 
     aSig = extractFloat32Frac( a );
@@ -2762,7 +2762,7 @@ int32 float64_to_int32_round_to_zero( float64 a STATUS_PARAM )
     flag aSign;
     int16 aExp, shiftCount;
     uint64_t aSig, savedASig;
-    int32 z;
+    int32_t z;
     a = float64_squash_input_denormal(a STATUS_VAR);
 
     aSig = extractFloat64Frac( a );
@@ -4248,7 +4248,7 @@ int32 floatx80_to_int32_round_to_zero( floatx80 a STATUS_PARAM )
     flag aSign;
     int32 aExp, shiftCount;
     uint64_t aSig, savedASig;
-    int32 z;
+    int32_t z;
 
     aSig = extractFloatx80Frac( a );
     aExp = extractFloatx80Exp( a );
@@ -5277,7 +5277,7 @@ int32 float128_to_int32_round_to_zero( float128 a STATUS_PARAM )
     flag aSign;
     int32 aExp, shiftCount;
     uint64_t aSig0, aSig1, savedASig;
-    int32 z;
+    int32_t z;
 
     aSig1 = extractFloat128Frac1( a );
     aSig0 = extractFloat128Frac0( a );
-- 
1.7.1

[Qemu-devel] [PATCH 3/3] softfloat: roundAndPackInt{32, 64}: Don't assume int32 is 32 bits

[Peter Maydell]

Fix code in roundAndPackInt32 that assumed that int32 was only
32 bits, by simply using int32_t instead. Fix the parallel bug
in roundAndPackInt64 as well, although that one is only theoretical
since it's unlikely that int64 will ever be more than 64 bits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 fpu/softfloat.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 08db899..e4ab9e1 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -117,7 +117,7 @@ static int32 roundAndPackInt32( flag zSign, uint64_t absZ STATUS_PARAM)
     int8 roundingMode;
     flag roundNearestEven;
     int8 roundIncrement, roundBits;
-    int32 z;
+    int32_t z;
 
     roundingMode = STATUS(float_rounding_mode);
     roundNearestEven = ( roundingMode == float_round_nearest_even );
@@ -166,7 +166,7 @@ static int64 roundAndPackInt64( flag zSign, uint64_t absZ0, uint64_t absZ1 STATU
 {
     int8 roundingMode;
     flag roundNearestEven, increment;
-    int64 z;
+    int64_t z;
 
     roundingMode = STATUS(float_rounding_mode);
     roundNearestEven = ( roundingMode == float_round_nearest_even );
-- 
1.7.1