[Qemu-devel] [PATCH] target-arm: Fix implementation of TLB invalidate operations

[Peter Maydell <peter.maydell@linaro.org>]

Fix some bugs in the implementation of the TLB invalidate
operations on ARM:
 * the 'invalidate all' op was not passing flush_global=1
   to tlb_flush(); this doesn't have a practical effect since
   tlb_flush() currently ignores that argument, but is
   semantically incorrect
 * 'invalidate by address for all ASIDs' was implemented as
   flushing the whole TLB, which invalidates much more than
   strictly necessary. Use tlb_flush_page() instead.
We also annotate the ops with the ARM ARM official acronyms.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |   13 ++++++-------
 1 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00458fc..f11279e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1610,18 +1610,17 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
         break;
     case 8: /* MMU TLB control.  */
         switch (op2) {
-        case 0: /* Invalidate all.  */
-            tlb_flush(env, 0);
+        case 0: /* Invalidate all (TLBIALL) */
+            tlb_flush(env, 1);
             break;
-        case 1: /* Invalidate single TLB entry.  */
+        case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
             tlb_flush_page(env, val & TARGET_PAGE_MASK);
             break;
-        case 2: /* Invalidate on ASID.  */
+        case 2: /* Invalidate by ASID (TLBIASID) */
             tlb_flush(env, val == 0);
             break;
-        case 3: /* Invalidate single entry on MVA.  */
-            /* ??? This is like case 1, but ignores ASID.  */
-            tlb_flush(env, 1);
+        case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
+            tlb_flush_page(env, val & TARGET_PAGE_MASK);
             break;
         default:
             goto bad_reg;
-- 
1.7.1