From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56917) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RoLMc-0003TZ-B9 for qemu-devel@nongnu.org; Fri, 20 Jan 2012 15:47:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RoLMb-0002GQ-81 for qemu-devel@nongnu.org; Fri, 20 Jan 2012 15:47:10 -0500 Received: from smtp191.dfw.emailsrvr.com ([67.192.241.191]:42821) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RoLMa-0002Fn-Qk for qemu-devel@nongnu.org; Fri, 20 Jan 2012 15:47:09 -0500 From: Mark Langsdorf Date: Fri, 20 Jan 2012 14:46:59 -0600 Message-Id: <1327092420-10814-6-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: <1327092420-10814-1-git-send-email-mark.langsdorf@calxeda.com> References: <1327092420-10814-1-git-send-email-mark.langsdorf@calxeda.com> Subject: [Qemu-devel] [PATCH v13 5/6] arm: store the config_base_register during cpu_reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: i.mitsyanko@gmail.com, peter.maydell@linaro.org, afaerber@suse.de, mark.langsdorf@calxeda.com, edgar.iglesias@gmail.com Long term, the config_base_register will be a QDM parameter. In the meantime, models that use it need to be able to preserve it across cpu_reset() calls. Signed-off-by: Mark Langsdorf --- Changes from v1-v12 Skipped target-arm/helper.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 00458fc..a14db43 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -255,6 +255,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) void cpu_reset(CPUARMState *env) { uint32_t id; + uint32_t tmp = 0; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -262,9 +263,15 @@ void cpu_reset(CPUARMState *env) } id = env->cp15.c0_cpuid; + if (env->cp15.c15_config_base_address) { + tmp = env->cp15.c15_config_base_address; + } memset(env, 0, offsetof(CPUARMState, breakpoints)); if (id) cpu_reset_model_id(env, id); + if (tmp) { + env->cp15.c15_config_base_address = tmp; + } #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ -- 1.7.5.4