From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:46150) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rq5DC-00074e-O4 for qemu-devel@nongnu.org; Wed, 25 Jan 2012 10:56:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rq5D4-00023P-QA for qemu-devel@nongnu.org; Wed, 25 Jan 2012 10:56:38 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:39836) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rq5D4-000238-I7 for qemu-devel@nongnu.org; Wed, 25 Jan 2012 10:56:30 -0500 From: Peter Maydell Date: Wed, 25 Jan 2012 15:27:43 +0000 Message-Id: <1327505265-5976-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1327505265-5976-1-git-send-email-peter.maydell@linaro.org> References: <1327505265-5976-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , Blue Swirl Cc: qemu-devel@nongnu.org From: Mark Langsdorf Long term, the config_base_register will be a QDM parameter. In the meantime, models that use it need to be able to preserve it across cpu_reset() calls. Signed-off-by: Mark Langsdorf Signed-off-by: Peter Maydell --- target-arm/helper.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index f6e998b..22e40fc 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -255,6 +255,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) void cpu_reset(CPUARMState *env) { uint32_t id; + uint32_t tmp = 0; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -262,9 +263,11 @@ void cpu_reset(CPUARMState *env) } id = env->cp15.c0_cpuid; + tmp = env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); if (id) cpu_reset_model_id(env, id); + env->cp15.c15_config_base_address = tmp; #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ -- 1.7.1