From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40632) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RrUnU-0006NP-TC for qemu-devel@nongnu.org; Sun, 29 Jan 2012 08:27:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RrUnQ-0000WF-Ip for qemu-devel@nongnu.org; Sun, 29 Jan 2012 08:27:56 -0500 Received: from cantor2.suse.de ([195.135.220.15]:50586 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RrUnP-0000Vt-Ud for qemu-devel@nongnu.org; Sun, 29 Jan 2012 08:27:52 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 29 Jan 2012 14:25:30 +0100 Message-Id: <1327843531-32403-7-git-send-email-afaerber@suse.de> In-Reply-To: <1327843531-32403-1-git-send-email-afaerber@suse.de> References: <1327843531-32403-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC 6/7] target-arm: Introduce QOM CPU and use for it CPUID lookup List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Create a CPU subclass, and register classes matching all CPU models. Don't name the file target-arm/cpu.c so that the user emulators can still easily pick up the base class in hw/cpu.c via VPATH. Make arm_cpu_list() enumerate CPU subclasses. Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the CPUID in the class. NB: CPUIDs were first introduced by Paul Brook in r1765 (2006). Signed-off-by: Andreas F=C3=A4rber Cc: Anthony Liguori Cc: Paul Brook Cc: Peter Maydell --- Makefile.target | 1 + target-arm/cpu-core.c | 268 +++++++++++++++++++++++++++++++++++++++++++= ++++++ target-arm/cpu-core.h | 33 ++++++ target-arm/helper.c | 80 ++++----------- 4 files changed, 324 insertions(+), 58 deletions(-) create mode 100644 target-arm/cpu-core.c create mode 100644 target-arm/cpu-core.h diff --git a/Makefile.target b/Makefile.target index 5d3470e..96043c4 100644 --- a/Makefile.target +++ b/Makefile.target @@ -80,6 +80,7 @@ endif libobj-$(TARGET_SPARC64) +=3D vis_helper.o libobj-$(CONFIG_NEED_MMU) +=3D mmu.o libobj-$(TARGET_ARM) +=3D neon_helper.o iwmmxt_helper.o +libobj-$(TARGET_ARM) +=3D cpu-core.o ifeq ($(TARGET_BASE_ARCH), sparc) libobj-y +=3D fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_he= lper.o libobj-y +=3D cpu_init.o diff --git a/target-arm/cpu-core.c b/target-arm/cpu-core.c new file mode 100644 index 0000000..9761d8e --- /dev/null +++ b/target-arm/cpu-core.c @@ -0,0 +1,268 @@ +/* + * QEMU ARM CPU core + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * Licensed under the terms of the GNU GPL version 2 + * or (at your option) any later version. + */ + +#include "cpu-core.h" +#include "qemu-common.h" + +/* CPU models */ + +static void arm926_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x41069265; +} + +static void arm946_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x41059461; +} + +static void arm1026_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x4106a262; +} + +static void arm1136_r0_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x4107b362; +} + +static void arm1136_r1_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x4117b363; +} + +static void arm1176_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x410fb767; +} + +static void arm11mpcore_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x410fb022; +} + +static void cortex_m3_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x410fc231; +} + +static void cortex_a8_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x410fc080; +} + +static void cortex_a9_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x410fc090; +} + +static void cortex_a15_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x412fc0f1; +} + +static void ti925t_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x54029252; +} + +static void sa1100_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x4401A11B; +} + +static void sa1110_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x6901B119; +} + +static void pxa250_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69052100; +} + +static void pxa255_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69052d00; +} + +static void pxa260_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69052903; +} + +static void pxa261_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69052d05; +} + +static void pxa262_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69052d06; +} + +static void pxa270_a0_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69054110; +} + +static void pxa270_a1_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69054111; +} + +static void pxa270_b0_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69054112; +} + +static void pxa270_b1_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69054113; +} + +static void pxa270_c0_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69054114; +} + +static void pxa270_c5_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0x69054117; +} + +static void arm_any_cpu_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k =3D ARM_CPU_CLASS(klass); + + k->id =3D 0xffffffff; +} + +struct ARMCPUDef { + const char *name; + void (*class_init)(ObjectClass *klass, void *data); +}; + +static const struct ARMCPUDef arm_cpu_models[] =3D { + { "arm926", arm926_class_init }, + { "arm946", arm946_class_init }, + { "arm1026", arm1026_class_init }, + /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + */ + { "arm1136-r2", arm1136_r0_class_init }, + { "arm1136", arm1136_r1_class_init }, + { "arm1176", arm1176_class_init }, + { "arm11mpcore", arm11mpcore_class_init }, + { "cortex-m3", cortex_m3_class_init }, + { "cortex-a8", cortex_a8_class_init }, + { "cortex-a9", cortex_a9_class_init }, + { "cortex-a15", cortex_a15_class_init }, + { "ti925t", ti925t_class_init }, + { "sa1100", sa1100_class_init }, + { "sa1110", sa1110_class_init }, + { "pxa250", pxa250_class_init }, + { "pxa255", pxa255_class_init }, + { "pxa260", pxa260_class_init }, + { "pxa261", pxa261_class_init }, + { "pxa262", pxa262_class_init }, + { "pxa270", pxa270_a0_class_init }, /* XXX just an alias */ + { "pxa270-a0", pxa270_a0_class_init }, + { "pxa270-a1", pxa270_a1_class_init }, + { "pxa270-b0", pxa270_b0_class_init }, + { "pxa270-b1", pxa270_b1_class_init }, + { "pxa270-c0", pxa270_c0_class_init }, + { "pxa270-c5", pxa270_c5_class_init }, + { "any", arm_any_cpu_class_init }, + { } +}; + +static void cpu_register(const struct ARMCPUDef *def) +{ + TypeInfo type =3D { + .name =3D def->name, + .parent =3D TYPE_ARM_CPU, + .instance_size =3D sizeof(ARMCPU), + .class_size =3D sizeof(ARMCPUClass), + .class_init =3D def->class_init, + }; + + type_register_static(&type); +} + +static TypeInfo arm_cpu_type_info =3D { + .name =3D TYPE_ARM_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(ARMCPU), + .abstract =3D true, + .class_size =3D sizeof(ARMCPUClass), +}; + +static void arm_cpu_types_init(void) +{ + const struct ARMCPUDef *def; + + type_register_static(&arm_cpu_type_info); + for (def =3D arm_cpu_models; def->name !=3D NULL; def++) { + cpu_register(def); + } +} + +processor_init(arm_cpu_types_init) diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h new file mode 100644 index 0000000..be4bbc3 --- /dev/null +++ b/target-arm/cpu-core.h @@ -0,0 +1,33 @@ +/* + * QEMU ARM CPU core + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * Licensed under the terms of the GNU GPL version 2 + * or (at your option) any later version. + */ +#ifndef QEMU_ARM_CPU_CORE_H +#define QEMU_ARM_CPU_CORE_H + +#include "qemu/cpu.h" + +#define TYPE_ARM_CPU "arm-cpu-core" +#define ARM_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU) +#define ARM_CPU(obj) \ + OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU) +#define ARM_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) + +typedef struct ARMCPUClass { + CPUClass parent_class; + + uint32_t id; +} ARMCPUClass; + +typedef struct ARMCPU { + CPU parent_obj; +} ARMCPU; + + +#endif diff --git a/target-arm/helper.c b/target-arm/helper.c index ea4f35f..ece9635 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -11,6 +11,7 @@ #include "hw/loader.h" #endif #include "sysemu.h" +#include "cpu-core.h" =20 static uint32_t cortexa15_cp15_c0_c1[8] =3D { 0x00001131, 0x00011011, 0x02010555, 0x00000000, @@ -51,8 +52,6 @@ static uint32_t arm1176_cp15_c0_c1[8] =3D static uint32_t arm1176_cp15_c0_c2[8] =3D { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; =20 -static uint32_t cpu_arm_find_by_name(const char *name); - static inline void set_feature(CPUARMState *env, int feature) { env->features |=3D 1u << feature; @@ -400,13 +399,16 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *= buf, int reg) =20 CPUARMState *cpu_arm_init(const char *cpu_model) { + ObjectClass *klass; + ARMCPUClass *cpu_class; CPUARMState *env; - uint32_t id; static int inited =3D 0; =20 - id =3D cpu_arm_find_by_name(cpu_model); - if (id =3D=3D 0) + klass =3D object_class_by_name(cpu_model); + if (klass =3D=3D NULL) { return NULL; + } + cpu_class =3D ARM_CPU_CLASS(klass); env =3D g_malloc0(sizeof(CPUARMState)); cpu_exec_init(env); if (tcg_enabled() && !inited) { @@ -415,7 +417,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model) } =20 env->cpu_model_str =3D cpu_model; - env->cp15.c0_cpuid =3D id; + env->cp15.c0_cpuid =3D cpu_class->id; cpu_reset(env); if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, @@ -431,66 +433,28 @@ CPUARMState *cpu_arm_init(const char *cpu_model) return env; } =20 -struct arm_cpu_t { - uint32_t id; - const char *name; +struct ARMCPUListState { + fprintf_function cpu_fprintf; + FILE *file; }; =20 -static const struct arm_cpu_t arm_cpu_names[] =3D { - { ARM_CPUID_ARM926, "arm926"}, - { ARM_CPUID_ARM946, "arm946"}, - { ARM_CPUID_ARM1026, "arm1026"}, - { ARM_CPUID_ARM1136, "arm1136"}, - { ARM_CPUID_ARM1136_R2, "arm1136-r2"}, - { ARM_CPUID_ARM1176, "arm1176"}, - { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, - { ARM_CPUID_CORTEXM3, "cortex-m3"}, - { ARM_CPUID_CORTEXA8, "cortex-a8"}, - { ARM_CPUID_CORTEXA9, "cortex-a9"}, - { ARM_CPUID_CORTEXA15, "cortex-a15" }, - { ARM_CPUID_TI925T, "ti925t" }, - { ARM_CPUID_PXA250, "pxa250" }, - { ARM_CPUID_SA1100, "sa1100" }, - { ARM_CPUID_SA1110, "sa1110" }, - { ARM_CPUID_PXA255, "pxa255" }, - { ARM_CPUID_PXA260, "pxa260" }, - { ARM_CPUID_PXA261, "pxa261" }, - { ARM_CPUID_PXA262, "pxa262" }, - { ARM_CPUID_PXA270, "pxa270" }, - { ARM_CPUID_PXA270_A0, "pxa270-a0" }, - { ARM_CPUID_PXA270_A1, "pxa270-a1" }, - { ARM_CPUID_PXA270_B0, "pxa270-b0" }, - { ARM_CPUID_PXA270_B1, "pxa270-b1" }, - { ARM_CPUID_PXA270_C0, "pxa270-c0" }, - { ARM_CPUID_PXA270_C5, "pxa270-c5" }, - { ARM_CPUID_ANY, "any"}, - { 0, NULL} -}; - -void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) +static void arm_cpu_list_entry(ObjectClass *klass, void *opaque) { - int i; + struct ARMCPUListState *s =3D opaque; =20 - (*cpu_fprintf)(f, "Available CPUs:\n"); - for (i =3D 0; arm_cpu_names[i].name; i++) { - (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name); - } + (*s->cpu_fprintf)(s->file, " %s\n", + object_class_get_name(klass)); } =20 -/* return 0 if not found */ -static uint32_t cpu_arm_find_by_name(const char *name) +void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) { - int i; - uint32_t id; + struct ARMCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; =20 - id =3D 0; - for (i =3D 0; arm_cpu_names[i].name; i++) { - if (strcmp(name, arm_cpu_names[i].name) =3D=3D 0) { - id =3D arm_cpu_names[i].id; - break; - } - } - return id; + (*cpu_fprintf)(f, "Available CPUs:\n"); + cpu_class_foreach(arm_cpu_list_entry, &s); } =20 void cpu_arm_close(CPUARMState *env) --=20 1.7.7