From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RsZnT-0004IZ-Bt for qemu-devel@nongnu.org; Wed, 01 Feb 2012 08:00:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RsZnD-0005QZ-Ht for qemu-devel@nongnu.org; Wed, 01 Feb 2012 08:00:19 -0500 Received: from cantor2.suse.de ([195.135.220.15]:37180 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RsZnC-0005M6-NC for qemu-devel@nongnu.org; Wed, 01 Feb 2012 08:00:07 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 1 Feb 2012 13:57:23 +0100 Message-Id: <1328101045-10717-7-git-send-email-afaerber@suse.de> In-Reply-To: <1328101045-10717-1-git-send-email-afaerber@suse.de> References: <1328101045-10717-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v2 6/8] target-arm: Embed CPUARMState in QOM ARMCPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook We g_malloc0()'ed CPUARMState ourself, and exec.c's cpu_copy() runs through cpu_init() as well, so we are at liberty to supply the CPUState any way we see fit. Having CPUARMState as field in the QOM CPU allows both to access env from an ARMCPU object and to access the QOM Object and its ObjectClass from an env pointer, in ARM code for now. The goal is to convert all CPUs to QOM and to use CPU objects in central places, especially once we have property support for Object. This will then allow to have TCG AREG0 point to target-specific fields where small immediate offsets are desired (as pointed out by rth) while allowing for common fields at known offsets from the base class. Having the CPUID in ARMCPUClass, we can set it from the instance_init function. Same for cpu_model_str, which is now the QOM class name. Make cpu_reset() call cpu_do_reset(). Signed-off-by: Andreas F=C3=A4rber Cc: Anthony Liguori Cc: Paul Brook Cc: Peter Maydell Cc: Richard Henderson --- target-arm/cpu-core.c | 13 +++++++++++++ target-arm/cpu-core.h | 11 +++++++++++ target-arm/helper.c | 15 ++++++++------- 3 files changed, 32 insertions(+), 7 deletions(-) diff --git a/target-arm/cpu-core.c b/target-arm/cpu-core.c index b255741..1caf9aa 100644 --- a/target-arm/cpu-core.c +++ b/target-arm/cpu-core.c @@ -135,6 +135,18 @@ static const ARMCPUInfo arm_cpus[] =3D { }, }; =20 +static void arm_cpu_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMCPUClass *cpu_class =3D ARM_CPU_GET_CLASS(obj); + + memset(&cpu->env, 0, sizeof(CPUARMState)); + cpu_exec_init(&cpu->env); + + cpu->env.cpu_model_str =3D object_get_typename(obj); + cpu->env.cp15.c0_cpuid =3D cpu_class->id; +} + static void arm_cpu_class_init(ObjectClass *klass, void *data) { ARMCPUClass *k =3D ARM_CPU_CLASS(klass); @@ -152,6 +164,7 @@ static void cpu_register(const ARMCPUInfo *info) .name =3D info->name, .parent =3D TYPE_ARM_CPU, .instance_size =3D sizeof(ARMCPU), + .instance_init =3D arm_cpu_initfn, .class_size =3D sizeof(ARMCPUClass), .class_init =3D arm_cpu_class_init, .class_data =3D (void *)info, diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h index ccc5503..cd3af77 100644 --- a/target-arm/cpu-core.h +++ b/target-arm/cpu-core.h @@ -10,6 +10,7 @@ #define QEMU_ARM_CPU_CORE_H =20 #include "qemu/cpu.h" +#include "cpu.h" =20 #define TYPE_ARM_CPU "arm-cpu" =20 @@ -39,7 +40,17 @@ typedef struct ARMCPUClass { */ typedef struct ARMCPU { CPU parent_obj; + + /* TODO Inline this and split off common state */ + CPUARMState env; } ARMCPU; =20 +static inline Object *arm_env_get_object(CPUARMState *env) +{ + return OBJECT((void *)(env) - offsetof(ARMCPU, env)); +} + +#define ENV_GET_OBJECT(e) arm_env_get_object(e) + =20 #endif diff --git a/target-arm/helper.c b/target-arm/helper.c index 3f34d8d..34b1d24 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -292,6 +292,8 @@ void cpu_reset(CPUARMState *env) log_cpu_state(env, 0); } =20 + cpu_do_reset(CPU(ENV_GET_OBJECT(env))); + id =3D env->cp15.c0_cpuid; tmp =3D env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); @@ -400,7 +402,7 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *bu= f, int reg) CPUARMState *cpu_arm_init(const char *cpu_model) { ObjectClass *klass; - ARMCPUClass *cpu_class; + ARMCPU *cpu; CPUARMState *env; static int inited =3D 0; =20 @@ -408,16 +410,14 @@ CPUARMState *cpu_arm_init(const char *cpu_model) if (klass =3D=3D NULL) { return NULL; } - cpu_class =3D ARM_CPU_CLASS(klass); - env =3D g_malloc0(sizeof(CPUARMState)); - cpu_exec_init(env); + cpu =3D ARM_CPU(object_new_with_type(klass->type)); + env =3D &cpu->env; + if (tcg_enabled() && !inited) { inited =3D 1; arm_translate_init(); } =20 - env->cpu_model_str =3D cpu_model; - env->cp15.c0_cpuid =3D cpu_class->id; cpu_reset(env); if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, @@ -459,7 +459,8 @@ void arm_cpu_list(FILE *f, fprintf_function cpu_fprin= tf) =20 void cpu_arm_close(CPUARMState *env) { - g_free(env); + Object *obj =3D ENV_GET_OBJECT(env); + object_delete(obj); } =20 static int bad_mode_switch(CPUState *env, int mode) --=20 1.7.7