From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:48473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rslo8-0004i0-GA for qemu-devel@nongnu.org; Wed, 01 Feb 2012 20:49:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rslo2-0005SP-Od for qemu-devel@nongnu.org; Wed, 01 Feb 2012 20:49:52 -0500 From: Alexander Graf Date: Thu, 2 Feb 2012 02:49:26 +0100 Message-Id: <1328147384-10387-4-git-send-email-agraf@suse.de> In-Reply-To: <1328147384-10387-1-git-send-email-agraf@suse.de> References: <1328147384-10387-1-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 03/21] PPC: Add IVOR 38-42 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: Blue Swirl , qemu-devel Developers , Aurelien Jarno Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06 from 38 - 42. Signed-off-by: Alexander Graf Reviewed-by: Andreas F=C3=A4rber --- target-ppc/cpu.h | 5 +++++ target-ppc/translate_init.c | 29 +++++++++++++++-------------- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 2d67d1f..6f4cdde 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1371,6 +1371,11 @@ static inline void cpu_clone_regs(CPUState *env, t= arget_ulong newsp) #define SPR_BOOKE_IVOR13 (0x19D) #define SPR_BOOKE_IVOR14 (0x19E) #define SPR_BOOKE_IVOR15 (0x19F) +#define SPR_BOOKE_IVOR38 (0x1B0) +#define SPR_BOOKE_IVOR39 (0x1B1) +#define SPR_BOOKE_IVOR40 (0x1B2) +#define SPR_BOOKE_IVOR41 (0x1B3) +#define SPR_BOOKE_IVOR42 (0x1B4) #define SPR_BOOKE_SPEFSCR (0x200) #define SPR_Exxx_BBEAR (0x201) #define SPR_Exxx_BBTAR (0x202) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 4d692d0..83348b5 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -526,26 +526,27 @@ static void spr_write_excp_prefix (void *opaque, in= t sprn, int gprn) static void spr_write_excp_vector (void *opaque, int sprn, int gprn) { DisasContext *ctx =3D opaque; + int sprn_offs; =20 if (sprn >=3D SPR_BOOKE_IVOR0 && sprn <=3D SPR_BOOKE_IVOR15) { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask)); - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn = - SPR_BOOKE_IVOR0])); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); + sprn_offs =3D sprn - SPR_BOOKE_IVOR0; } else if (sprn >=3D SPR_BOOKE_IVOR32 && sprn <=3D SPR_BOOKE_IVOR37)= { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask)); - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn = - SPR_BOOKE_IVOR32 + 32])); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); + sprn_offs =3D sprn - SPR_BOOKE_IVOR32 + 32; + } else if (sprn >=3D SPR_BOOKE_IVOR38 && sprn <=3D SPR_BOOKE_IVOR42)= { + sprn_offs =3D sprn - SPR_BOOKE_IVOR38 + 38; } else { printf("Trying to write an unknown exception vector %d %03x\n", sprn, sprn); gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); + return; } + + TCGv t0 =3D tcg_temp_new(); + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask)); + tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn_offs= ])); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); } #endif =20 @@ -1434,8 +1435,8 @@ static void gen_spr_BookE (CPUPPCState *env, uint64= _t ivor_mask) SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_= IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_= IVORxx, SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_= IVOR35, - SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_= IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_= IVORxx, + SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_= IVOR39, + SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_= IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_= IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_= IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_= IVORxx, --=20 1.6.0.2