From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:48725) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RsloO-00056d-On for qemu-devel@nongnu.org; Wed, 01 Feb 2012 20:50:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rslo3-0005TE-Ey for qemu-devel@nongnu.org; Wed, 01 Feb 2012 20:50:02 -0500 From: Alexander Graf Date: Thu, 2 Feb 2012 02:49:31 +0100 Message-Id: <1328147384-10387-9-git-send-email-agraf@suse.de> In-Reply-To: <1328147384-10387-1-git-send-email-agraf@suse.de> References: <1328147384-10387-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 08/21] PPC: booke: add tlbnps handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: Blue Swirl , qemu-devel Developers , Aurelien Jarno When using MAV 2.0 TLB registers, we have another range of TLB registers available to read the supported page sizes from. Add SPR definitions for those and add a helper function that we can use to receive such a bitmap even when using MAV 1.0. Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 6f4cdde..1026254 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1355,6 +1355,10 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) #define SPR_BOOKE_DVC2 (0x13F) #define SPR_BOOKE_TSR (0x150) #define SPR_BOOKE_TCR (0x154) +#define SPR_BOOKE_TLB0PS (0x158) +#define SPR_BOOKE_TLB1PS (0x159) +#define SPR_BOOKE_TLB2PS (0x15A) +#define SPR_BOOKE_TLB3PS (0x15B) #define SPR_BOOKE_IVOR0 (0x190) #define SPR_BOOKE_IVOR1 (0x191) #define SPR_BOOKE_IVOR2 (0x192) @@ -2116,6 +2120,27 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn, return &env->tlb.tlbm[r]; } +/* returns bitmap of supported page sizes for a given TLB */ +static inline uint32_t booke206_tlbnps(CPUState *env, const int tlbn) +{ + bool mav2 = false; + uint32_t ret = 0; + + if (mav2) { + ret = env->spr[SPR_BOOKE_TLB0PS + tlbn]; + } else { + uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; + uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; + uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; + int i; + for (i = min; i <= max; i++) { + ret |= (1 << (i << 1)); + } + } + + return ret; +} + #endif extern void (*cpu_ppc_hypercall)(CPUState *); -- 1.6.0.2