From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44724) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RuW8N-0004Ax-VZ for qemu-devel@nongnu.org; Mon, 06 Feb 2012 16:30:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RuW8M-0001LK-BJ for qemu-devel@nongnu.org; Mon, 06 Feb 2012 16:29:59 -0500 Received: from smtp1-g21.free.fr ([212.27.42.1]:33815) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RuW8L-0001KH-Ak for qemu-devel@nongnu.org; Mon, 06 Feb 2012 16:29:58 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 6 Feb 2012 22:29:06 +0100 Message-Id: <1328563752-3976-6-git-send-email-hpoussin@reactos.org> In-Reply-To: <1328563752-3976-1-git-send-email-hpoussin@reactos.org> References: <1328563752-3976-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v4 05/11] fdc: add CCR (Configuration Control Register) write register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Kevin Wolf , =?UTF-8?q?Herv=C3=A9=20Poussineau?= DIR and CCR registers share the same address ; DIR is read-only while CCR is write-only CCR register is used to change media transfer rate, which will be checked in following changes. Signed-off-by: Herv=C3=A9 Poussineau --- hw/fdc.c | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/hw/fdc.c b/hw/fdc.c index 060ca84..2bad97b 100644 --- a/hw/fdc.c +++ b/hw/fdc.c @@ -224,6 +224,7 @@ static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_= t value); static uint32_t fdctrl_read_data(FDCtrl *fdctrl); static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); +static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); =20 enum { FD_DIR_WRITE =3D 0, @@ -248,6 +249,7 @@ enum { FD_REG_DSR =3D 0x04, FD_REG_FIFO =3D 0x05, FD_REG_DIR =3D 0x07, + FD_REG_CCR =3D 0x07, }; =20 enum { @@ -491,6 +493,9 @@ static void fdctrl_write (void *opaque, uint32_t reg,= uint32_t value) case FD_REG_FIFO: fdctrl_write_data(fdctrl, value); break; + case FD_REG_CCR: + fdctrl_write_ccr(fdctrl, value); + break; default: break; } @@ -881,6 +886,23 @@ static void fdctrl_write_rate(FDCtrl *fdctrl, uint32= _t value) fdctrl->dsr =3D value; } =20 +/* Configuration control register: 0x07 (write) */ +static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) +{ + /* Reset mode */ + if (!(fdctrl->dor & FD_DOR_nRESET)) { + FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); + return; + } + FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", val= ue); + + /* Only the rate selection bits used in AT mode, and we + * store those in the DSR. + */ + fdctrl->dsr =3D (fdctrl->dsr & ~FD_DSR_DRATEMASK) | + (value & FD_DSR_DRATEMASK); +} + static int fdctrl_media_changed(FDrive *drv) { int ret; --=20 1.7.8.3