From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 1/7] cpu models: reorder flag list to match bit order
Date: Fri, 17 Feb 2012 14:41:19 -0200 [thread overview]
Message-ID: <1329496885-31961-2-git-send-email-ehabkost@redhat.com> (raw)
In-Reply-To: <1329496885-31961-1-git-send-email-ehabkost@redhat.com>
This will make it easier to review and change the flag list in the future.
No behaviour change should be introduced by this, as it is just changing
the flag order on the config file.
To make sure the flag sets are really not changed by this patch, I have
used the following stupid script to compare the flag values in the
config files:
https://gist.github.com/1004885
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
sysconfigs/target/target-x86_64.conf | 36 +++++++++++++++++-----------------
1 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 43ad282..6720778 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -7,9 +7,9 @@
family = "6"
model = "2"
stepping = "3"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 ssse3"
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu lm syscall nx"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "ssse3 sse3"
+ extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
@@ -21,9 +21,9 @@
family = "6"
model = "2"
stepping = "3"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16 ssse3 sse4.1"
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu lm syscall nx"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "sse4.1 cx16 ssse3 sse3"
+ extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
@@ -35,9 +35,9 @@
family = "6"
model = "2"
stepping = "3"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16 ssse3 sse4.1 sse4.2 popcnt"
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu lm syscall nx"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
+ extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
@@ -49,9 +49,9 @@
family = "15"
model = "6"
stepping = "1"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "sse3"
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu lm syscall nx"
+ extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
# extfeature_ecx = ""
xlevel = "0x80000008"
model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
@@ -63,9 +63,9 @@
family = "15"
model = "6"
stepping = "1"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16"
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu lm syscall nx rdtscp"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "cx16 sse3"
+ extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_ecx = "svm lahf_lm"
xlevel = "0x80000008"
model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
@@ -77,10 +77,10 @@
family = "15"
model = "6"
stepping = "1"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16 monitor popcnt"
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu lm syscall nx rdtscp"
- extfeature_ecx = "svm sse4a abm misalignsse lahf_lm"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "popcnt cx16 monitor sse3"
+ extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+ extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
xlevel = "0x80000008"
model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
--
1.7.3.2
next prev parent reply other threads:[~2012-02-17 16:41 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-17 16:41 [Qemu-devel] [PATCH 0/7] cpu model bug fixes and definition corrections (v3) Eduardo Habkost
2012-02-17 16:41 ` Eduardo Habkost [this message]
2012-02-17 16:41 ` [Qemu-devel] [PATCH 2/7] cpu flags: aliases: pclmuldq|pclmulqdq and ffxsr|fxsr_opt Eduardo Habkost
2012-02-17 16:41 ` [Qemu-devel] [PATCH 3/7] cpu defs: use Intel flag names for Intel models (v2) Eduardo Habkost
2012-02-17 16:41 ` [Qemu-devel] [PATCH 4/7] cpu defs: add pse36, mca, mtrr to AMD CPU definitions (v2) Eduardo Habkost
2012-02-17 16:41 ` [Qemu-devel] [PATCH 5/7] cpu defs: remove replicated flags from Intel (v2) Eduardo Habkost
2012-02-17 16:41 ` [Qemu-devel] [PATCH 6/7] add Westmere as a qemu cpu model (v2) Eduardo Habkost
2012-02-17 16:41 ` [Qemu-devel] [PATCH 7/7] cpu defs: uncomment empty extfeatures_ecx definition for Opteron_G1 (v2) Eduardo Habkost
2012-02-24 15:31 ` [Qemu-devel] [PATCH 0/7] cpu model bug fixes and definition corrections (v3) Anthony Liguori
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