[Qemu-devel] [PATCH] target-arm: Fix typo in ARM946 cp15 c5 handling

[Qemu-devel] [PATCH] target-arm: Fix typo in ARM946 cp15 c5 handling

[Peter Maydell]

Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling
(instruction access permission bits) that meant it would
return the data access permission bits by mistake.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
(Yeah, it says ARM_FEATURE_MPU but actually (a) the only MPU
core we support is the 946 and (b) these registers are 946
specific -- in PMSAv6 and v7 this encoding is the IFSR, the
same as it is for VMSA.)

 target-arm/helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4929372..8e6da06 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2030,7 +2030,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
             return env->cp15.c5_data;
         case 1:
             if (arm_feature(env, ARM_FEATURE_MPU))
-                return simple_mpu_ap_bits(env->cp15.c5_data);
+                return simple_mpu_ap_bits(env->cp15.c5_insn);
             return env->cp15.c5_insn;
         case 2:
             if (!arm_feature(env, ARM_FEATURE_MPU))
-- 
1.7.1