[Qemu-devel] [Seabios] [PATCH 1/6] Adding new structures

[Alexey Korolev <alexey.korolev@endace.com>]

This patch introduces two structures instead of old pci_bus one.
The pci_region structure describes one bus region. It includes a list 
of pci_region_entries and base address. 
Number of pci_region structures can be calculated:
PCI_REGION_TYPE_COUNT * number of busses.
Extra two regions can be added if we need 64bit address ranges.

The pci_region_entry describes PCI BAR resource or downstream PCI region (bridge region).
Each entry should be assigned to a particular pci_region. If the entry describes a bridge
region, it provides pci_region to downstream devices.
Having this we can easily build topology and migrate entries if necessary.


Signed-off-by: Alexey Korolev  <alexey.korolev@endace.com>

---
 src/pci.h     |    6 ------
 src/pciinit.c |   37 ++++++++++++++++++++++---------------
 2 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/src/pci.h b/src/pci.h
index a2a5a4c..8fa064f 100644
--- a/src/pci.h
+++ b/src/pci.h
@@ -51,12 +51,6 @@ struct pci_device {
     u8 prog_if, revision;
     u8 header_type;
     u8 secondary_bus;
-    struct {
-        u32 addr;
-        u32 size;
-        int is64;
-    } bars[PCI_NUM_REGIONS];
-
     // Local information on device.
     int have_driver;
 };
diff --git a/src/pciinit.c b/src/pciinit.c
index 9f3fdd4..2e5416c 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -31,18 +31,24 @@ static const char *region_type_name[] = {
     [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
 };
 
-struct pci_bus {
-    struct {
-        /* pci region stats */
-        u32 count[32 - PCI_MEM_INDEX_SHIFT];
-        u32 sum, max;
-        /* seconday bus region sizes */
-        u32 size;
-        /* pci region assignments */
-        u32 bases[32 - PCI_MEM_INDEX_SHIFT];
-        u32 base;
-    } r[PCI_REGION_TYPE_COUNT];
-    struct pci_device *bus_dev;
+struct pci_region;
+struct pci_region_entry {
+    struct pci_device *dev;
+    int bar;
+    u64 base;
+    u64 size;
+    int is64bit;
+    enum pci_region_type type;
+    struct pci_region *this_region;
+    struct pci_region *parent_region;
+    struct pci_region_entry *next;
+    struct pci_region_entry **pprev;
+};
+
+struct pci_region {
+    struct pci_region_entry *list;
+    struct pci_region_entry *this_entry;
+    u64 base;
 };
 
 static int pci_size_to_index(u32 size, enum pci_region_type type)
@@ -582,12 +588,13 @@ pci_setup(void)
     pci_probe_devices();
 
     dprintf(1, "=== PCI new allocation pass #1 ===\n");
-    struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
-    if (!busses) {
+    int num_regions = (MaxPCIBus + 1) * PCI_REGION_TYPE_COUNT;
+    struct pci_region *regions = malloc_tmp(sizeof(*regions) * num_regions);
+    if (!regions) {
         warn_noalloc();
         return;
     }
-    memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
+    memset(regions, 0, sizeof(*regions) * num_regions);
     pci_bios_check_devices(busses);
     if (pci_bios_init_root_regions(&busses[0], start, end) != 0) {
         panic("PCI: out of address space\n");
-- 
1.7.5.4