From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: Paul Brook <paul@codesourcery.com>, patches@linaro.org
Subject: [Qemu-devel] [PATCH] target-arm: Clear IT bits when taking exceptions in v7M
Date: Fri, 2 Mar 2012 10:56:49 +0000 [thread overview]
Message-ID: <1330685809-7513-1-git-send-email-peter.maydell@linaro.org> (raw)
When taking an exception for an M profile core, we must clear
the IT bits. Since the IT bits are cached in env->condexec_bits
we must clear them there: writing the bits in env->uncached_cpsr
has no effect. (Reported as LP:944645.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4929372..71fcc41 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -882,7 +882,8 @@ static void do_interrupt_v7m(CPUARMState *env)
v7m_push(env, env->regs[1]);
v7m_push(env, env->regs[0]);
switch_v7m_sp(env, 0);
- env->uncached_cpsr &= ~CPSR_IT;
+ /* Clear IT bits */
+ env->condexec_bits = 0;
env->regs[14] = lr;
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
env->regs[15] = addr & 0xfffffffe;
--
1.7.1
reply other threads:[~2012-03-02 10:57 UTC|newest]
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