From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41994) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3QAX-00031O-Jp for qemu-devel@nongnu.org; Fri, 02 Mar 2012 05:57:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S3QAV-0006P5-SR for qemu-devel@nongnu.org; Fri, 02 Mar 2012 05:57:01 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:33242) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3QAV-0006Og-Kp for qemu-devel@nongnu.org; Fri, 02 Mar 2012 05:56:59 -0500 From: Peter Maydell Date: Fri, 2 Mar 2012 10:56:49 +0000 Message-Id: <1330685809-7513-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH] target-arm: Clear IT bits when taking exceptions in v7M List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paul Brook , patches@linaro.org When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: Peter Maydell --- target-arm/helper.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4929372..71fcc41 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -882,7 +882,8 @@ static void do_interrupt_v7m(CPUARMState *env) v7m_push(env, env->regs[1]); v7m_push(env, env->regs[0]); switch_v7m_sp(env, 0); - env->uncached_cpsr &= ~CPSR_IT; + /* Clear IT bits */ + env->condexec_bits = 0; env->regs[14] = lr; addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4); env->regs[15] = addr & 0xfffffffe; -- 1.7.1