[Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR in ARMCPUClass

["Andreas Färber" <afaerber@suse.de>]

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu-qom.h |    1 +
 target-arm/cpu.c     |   19 +++++++++++++++++++
 target-arm/cpu.h     |    3 ---
 target-arm/helper.c  |   17 -----------------
 4 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 722d164..3832986 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -51,6 +51,7 @@ typedef struct ARMCPUClass {
         uint32_t c0_cachetype;
         uint32_t c0_c1[8];
         uint32_t c0_c2[8];
+        uint32_t c1_sys;
     } cp15;
 
     uint32_t features;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index c7cf46d..2f3190a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -50,6 +50,9 @@ static void arm_cpu_reset(CPUState *c)
     memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
     memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t));
 
+    /* Genuine reset */
+    env->cp15.c1_sys = klass->cp15.c1_sys;
+
 #if defined(CONFIG_USER_ONLY)
     env->uncached_cpsr = ARM_CPU_MODE_USR;
     /* For user mode we must enable access to coprocessors */
@@ -173,6 +176,7 @@ typedef struct ARMCPUInfo {
     uint32_t cp15_c0_cachetype;
     uint32_t cp15_c0_c1[8];
     uint32_t cp15_c0_c2[8];
+    uint32_t cp15_c1_sys;
     uint32_t features;
     void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
 } ARMCPUInfo;
@@ -193,6 +197,7 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
     k->cp15.c0_cachetype = r1_class->cp15.c0_cachetype;
     memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
     memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
+    k->cp15.c1_sys = r1_class->cp15.c1_sys;
 }
 
 static void ti925t_reset(CPUState *c)
@@ -214,12 +219,15 @@ static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
 
 static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
 {
+    k->cp15.c1_sys = 0x00000070;
+
     set_class_feature(k, ARM_FEATURE_STRONGARM);
 }
 
 static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
 {
     k->cp15.c0_cachetype = 0xd172172;
+    k->cp15.c1_sys = 0x00000078;
 
     set_class_feature(k, ARM_FEATURE_V5);
     set_class_feature(k, ARM_FEATURE_XSCALE);
@@ -228,6 +236,7 @@ static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
 static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
 {
     k->cp15.c0_cachetype = 0xd172172;
+    k->cp15.c1_sys = 0x00000078;
 
     set_class_feature(k, ARM_FEATURE_V5);
     set_class_feature(k, ARM_FEATURE_XSCALE);
@@ -239,6 +248,7 @@ static const ARMCPUInfo arm_cpus[] = {
         .name = "arm926",
         .id = 0x41069265,
         .cp15_c0_cachetype = 0x1dd20d2,
+        .cp15_c1_sys = 0x00090078,
         .features = ARM_FEATURE(V5) |
                     ARM_FEATURE(VFP),
     },
@@ -246,6 +256,7 @@ static const ARMCPUInfo arm_cpus[] = {
         .name = "arm946",
         .id = 0x41059461,
         .cp15_c0_cachetype = 0x0f004006,
+        .cp15_c1_sys = 0x00000078,
         .features = ARM_FEATURE(V5) |
                     ARM_FEATURE(MPU),
     },
@@ -253,6 +264,7 @@ static const ARMCPUInfo arm_cpus[] = {
         .name = "arm1026",
         .id = 0x4106a262,
         .cp15_c0_cachetype = 0x1dd20d2,
+        .cp15_c1_sys = 0x00090078,
         .features = ARM_FEATURE(V5) |
                     ARM_FEATURE(VFP) |
                     ARM_FEATURE(AUXCR),
@@ -278,6 +290,7 @@ static const ARMCPUInfo arm_cpus[] = {
             0x00140011, 0x12002111, 0x11231111, 0x01102131,
             0x141, 0, 0, 0
         },
+        .cp15_c1_sys = 0x00050078,
         .features = ARM_FEATURE(V6) |
                     ARM_FEATURE(VFP),
     },
@@ -293,6 +306,7 @@ static const ARMCPUInfo arm_cpus[] = {
             0x0140011, 0x12002111, 0x11231121, 0x01102131,
             0x01141, 0, 0, 0
         },
+        .cp15_c1_sys = 0x00050078,
         .features = ARM_FEATURE(V6K) |
                     ARM_FEATURE(VFP) |
                     ARM_FEATURE(VAPA),
@@ -331,6 +345,7 @@ static const ARMCPUInfo arm_cpus[] = {
             0x00101111, 0x12112111, 0x21232031, 0x11112131,
             0x00111142, 0, 0, 0
         },
+        .cp15_c1_sys = 0x00c50078,
         .features = ARM_FEATURE(V7) |
                     ARM_FEATURE(VFP3) |
                     ARM_FEATURE(NEON) |
@@ -348,6 +363,7 @@ static const ARMCPUInfo arm_cpus[] = {
             0x00101111, 0x13112111, 0x21232041, 0x11112131,
             0x00111142, 0, 0, 0
         },
+        .cp15_c1_sys = 0x00c50078,
         .features = ARM_FEATURE(V7) |
                     ARM_FEATURE(VFP3) |
                     ARM_FEATURE(VFP_FP16) |
@@ -371,6 +387,7 @@ static const ARMCPUInfo arm_cpus[] = {
             0x02101110, 0x13112111, 0x21232041, 0x11112131,
             0x10011142, 0, 0, 0
         },
+        .cp15_c1_sys = 0x00c50078,
         .features = ARM_FEATURE(V7) |
                     ARM_FEATURE(VFP4) |
                     ARM_FEATURE(VFP_FP16) |
@@ -384,6 +401,7 @@ static const ARMCPUInfo arm_cpus[] = {
         .name = "ti925t",
         .id = 0x54029252,
         .cp15_c0_cachetype = 0x5109149,
+        .cp15_c1_sys = 0x00000070,
         .features = ARM_FEATURE(V4T) |
                     ARM_FEATURE(OMAPCP),
         .class_init = ti925t_class_init,
@@ -493,6 +511,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
     k->cp15.c0_cachetype = info->cp15_c0_cachetype;
     memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
     memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
+    k->cp15.c1_sys = info->cp15_c1_sys;
     k->features = info->features;
 
     if (info->class_init != NULL) {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 48d42b7..66e62e2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -404,11 +404,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 
 #define ARM_CPUID_ARM1026     0x4106a262
 #define ARM_CPUID_ARM926      0x41069265
-#define ARM_CPUID_ARM946      0x41059461
 #define ARM_CPUID_TI915T      0x54029152
 #define ARM_CPUID_TI925T      0x54029252
-#define ARM_CPUID_SA1100      0x4401A11B
-#define ARM_CPUID_SA1110      0x6901B119
 #define ARM_CPUID_PXA250      0x69052100
 #define ARM_CPUID_PXA255      0x69052d00
 #define ARM_CPUID_PXA260      0x69052903
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 14ed890..548d8cf 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,14 +10,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     switch (id) {
     case ARM_CPUID_ARM926:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
-        env->cp15.c1_sys = 0x00090078;
-        break;
-    case ARM_CPUID_ARM946:
-        env->cp15.c1_sys = 0x00000078;
         break;
     case ARM_CPUID_ARM1026:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
-        env->cp15.c1_sys = 0x00090078;
         break;
     case ARM_CPUID_ARM1136:
         /* This is the 1136 r1, which is a v6K core */
@@ -34,13 +29,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
-        env->cp15.c1_sys = 0x00050078;
         break;
     case ARM_CPUID_ARM1176:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
-        env->cp15.c1_sys = 0x00050078;
         break;
     case ARM_CPUID_ARM11MPCORE:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
@@ -55,7 +48,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
         env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
         env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
-        env->cp15.c1_sys = 0x00c50078;
         break;
     case ARM_CPUID_CORTEXA9:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
@@ -64,7 +56,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
         env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
         env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
-        env->cp15.c1_sys = 0x00c50078;
         break;
     case ARM_CPUID_CORTEXA15:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
@@ -74,11 +65,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
         env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
         env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
-        env->cp15.c1_sys = 0x00c50078;
         break;
     case ARM_CPUID_TI915T:
     case ARM_CPUID_TI925T:
-        env->cp15.c1_sys = 0x00000070;
         env->cp15.c15_i_max = 0x000;
         env->cp15.c15_i_min = 0xff0;
         break;
@@ -88,7 +77,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     case ARM_CPUID_PXA261:
     case ARM_CPUID_PXA262:
         /* JTAG_ID is ((id << 28) | 0x09265013) */
-        env->cp15.c1_sys = 0x00000078;
         break;
     case ARM_CPUID_PXA270_A0:
     case ARM_CPUID_PXA270_A1:
@@ -98,11 +86,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     case ARM_CPUID_PXA270_C5:
         /* JTAG_ID is ((id << 28) | 0x09265013) */
         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
-        env->cp15.c1_sys = 0x00000078;
-        break;
-    case ARM_CPUID_SA1100:
-    case ARM_CPUID_SA1110:
-        env->cp15.c1_sys = 0x00000070;
         break;
     default:
         break;
-- 
1.7.7