From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYW-0006Jw-NZ for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6PYU-0001QZ-3F for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:08 -0500 Received: from cantor2.suse.de ([195.135.220.15]:42636 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYT-0001PJ-Te for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:06 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 10 Mar 2012 17:53:43 +0100 Message-Id: <1331398436-20761-8-git-send-email-afaerber@suse.de> In-Reply-To: <1331398436-20761-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331398436-20761-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Having moved the reset code for some CPUs to class_init, we can drop some of the cases in the switch. Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- target-arm/cpu.h | 2 -- target-arm/helper.c | 5 ----- 2 files changed, 0 insertions(+), 7 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d14fb01..48d42b7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -427,8 +427,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_CORTEXA8 0x410fc080 #define ARM_CPUID_CORTEXA9 0x410fc090 #define ARM_CPUID_CORTEXA15 0x412fc0f1 -#define ARM_CPUID_CORTEXM3 0x410fc231 -#define ARM_CPUID_ANY 0xffffffff =20 #if defined(CONFIG_USER_ONLY) #define TARGET_PAGE_BITS 12 diff --git a/target-arm/helper.c b/target-arm/helper.c index 0dd6065..59a9812 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -136,10 +136,6 @@ static void cpu_reset_model_id(CPUARMState *env, uin= t32_t id) env->cp15.c0_ccsid[2] =3D 0x711fe07a; /* 4096K L2 unified cache = */ env->cp15.c1_sys =3D 0x00c50078; break; - case ARM_CPUID_CORTEXM3: - break; - case ARM_CPUID_ANY: /* For userspace emulation. */ - break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: env->cp15.c0_cachetype =3D 0x5109149; @@ -172,7 +168,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint= 32_t id) env->cp15.c1_sys =3D 0x00000070; break; default: - cpu_abort(env, "Bad CPU ID: %x\n", id); break; } } --=20 1.7.7