From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S70hg-0005wV-1V for qemu-devel@nongnu.org; Mon, 12 Mar 2012 04:34:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S70hF-00039X-5K for qemu-devel@nongnu.org; Mon, 12 Mar 2012 04:34:01 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:52135) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S70hE-00035p-NW for qemu-devel@nongnu.org; Mon, 12 Mar 2012 04:33:37 -0400 Received: by mail-iy0-f173.google.com with SMTP id j26so7248932iaf.4 for ; Mon, 12 Mar 2012 01:33:35 -0700 (PDT) From: Jia Liu Date: Mon, 12 Mar 2012 16:32:39 +0800 Message-Id: <1331541159-5218-5-git-send-email-proljc@gmail.com> In-Reply-To: <1331541159-5218-1-git-send-email-proljc@gmail.com> References: <1331541159-5218-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH 4/4] add MIPS DSP testcase List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net This patch is the testcases of MIPS ASE DSP. Signed-off-by: Jia Liu --- tests/tcg/mips/mips32-dsp/Makefile | 133 ++++++++++++++++++++++++ tests/tcg/mips/mips32-dsp/absq_s_ph.c | 28 +++++ tests/tcg/mips/mips32-dsp/absq_s_w.c | 35 ++++++ tests/tcg/mips/mips32-dsp/addq_ph.c | 29 +++++ tests/tcg/mips/mips32-dsp/addq_s_ph.c | 29 +++++ tests/tcg/mips/mips32-dsp/addsc.c | 28 +++++ tests/tcg/mips/mips32-dsp/addu_qb.c | 28 +++++ tests/tcg/mips/mips32-dsp/addu_s_qb.c | 28 +++++ tests/tcg/mips/mips32-dsp/addwc.c | 28 +++++ tests/tcg/mips/mips32-dsp/bitrev.c | 18 +++ tests/tcg/mips/mips32-dsp/bposge32.c | 42 ++++++++ tests/tcg/mips/mips32-dsp/cmp_eq_ph.c | 33 ++++++ tests/tcg/mips/mips32-dsp/cmp_le_ph.c | 33 ++++++ tests/tcg/mips/mips32-dsp/cmp_lt_ph.c | 33 ++++++ tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c | 29 +++++ tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c | 29 +++++ tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c | 29 +++++ tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c | 33 ++++++ tests/tcg/mips/mips32-dsp/cmpu_le_qb.c | 33 ++++++ tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c | 33 ++++++ tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c | 29 +++++ tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c | 29 +++++ tests/tcg/mips/mips32-dsp/dpau_h_qbl.c | 25 +++++ tests/tcg/mips/mips32-dsp/dpau_h_qbr.c | 25 +++++ tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c | 25 +++++ tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c | 29 +++++ tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c | 25 +++++ tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c | 25 +++++ tests/tcg/mips/mips32-dsp/extp.c | 42 ++++++++ tests/tcg/mips/mips32-dsp/extpdp.c | 44 ++++++++ tests/tcg/mips/mips32-dsp/extpdpv.c | 45 ++++++++ tests/tcg/mips/mips32-dsp/extpv.c | 43 ++++++++ tests/tcg/mips/mips32-dsp/extr_r_w.c | 23 ++++ tests/tcg/mips/mips32-dsp/extr_rs_w.c | 23 ++++ tests/tcg/mips/mips32-dsp/extr_s_h.c | 23 ++++ tests/tcg/mips/mips32-dsp/extr_w.c | 23 ++++ tests/tcg/mips/mips32-dsp/extrv_r_w.c | 27 +++++ tests/tcg/mips/mips32-dsp/extrv_rs_w.c | 27 +++++ tests/tcg/mips/mips32-dsp/extrv_s_h.c | 27 +++++ tests/tcg/mips/mips32-dsp/extrv_w.c | 27 +++++ tests/tcg/mips/mips32-dsp/insv.c | 21 ++++ tests/tcg/mips/mips32-dsp/lbux.c | 21 ++++ tests/tcg/mips/mips32-dsp/lhx.c | 21 ++++ tests/tcg/mips/mips32-dsp/lwx.c | 21 ++++ tests/tcg/mips/mips32-dsp/madd.c | 29 +++++ tests/tcg/mips/mips32-dsp/maddu.c | 29 +++++ tests/tcg/mips/mips32-dsp/maq_s_w_phl.c | 29 +++++ tests/tcg/mips/mips32-dsp/maq_s_w_phr.c | 29 +++++ tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c | 29 +++++ tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c | 29 +++++ tests/tcg/mips/mips32-dsp/mfhi.c | 19 ++++ tests/tcg/mips/mips32-dsp/mflo.c | 19 ++++ tests/tcg/mips/mips32-dsp/modsub.c | 28 +++++ tests/tcg/mips/mips32-dsp/msub.c | 28 +++++ tests/tcg/mips/mips32-dsp/msubu.c | 28 +++++ tests/tcg/mips/mips32-dsp/mthi.c | 19 ++++ tests/tcg/mips/mips32-dsp/mthlip.c | 32 ++++++ tests/tcg/mips/mips32-dsp/mtlo.c | 19 ++++ tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c | 38 +++++++ tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c | 23 ++++ tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c | 23 ++++ tests/tcg/mips/mips32-dsp/mulq_rs_ph.c | 23 ++++ tests/tcg/mips/mips32-dsp/mult.c | 22 ++++ tests/tcg/mips/mips32-dsp/multu.c | 22 ++++ tests/tcg/mips/mips32-dsp/packrl_ph.c | 19 ++++ tests/tcg/mips/mips32-dsp/pick_ph.c | 21 ++++ tests/tcg/mips/mips32-dsp/pick_qb.c | 21 ++++ tests/tcg/mips/mips32-dsp/preceq_w_phl.c | 18 +++ tests/tcg/mips/mips32-dsp/preceq_w_phr.c | 18 +++ tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c | 18 +++ tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c | 18 +++ tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c | 18 +++ tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c | 18 +++ tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c | 18 +++ tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c | 18 +++ tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c | 18 +++ tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c | 18 +++ tests/tcg/mips/mips32-dsp/precrq_ph_w.c | 19 ++++ tests/tcg/mips/mips32-dsp/precrq_qb_ph.c | 19 ++++ tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c | 19 ++++ tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c | 19 ++++ tests/tcg/mips/mips32-dsp/raddu_w_qb.c | 18 +++ tests/tcg/mips/mips32-dsp/rddsp.c | 52 +++++++++ tests/tcg/mips/mips32-dsp/repl_ph.c | 21 ++++ tests/tcg/mips/mips32-dsp/repl_qb.c | 14 +++ tests/tcg/mips/mips32-dsp/replv_ph.c | 17 +++ tests/tcg/mips/mips32-dsp/replv_qb.c | 17 +++ tests/tcg/mips/mips32-dsp/shilo.c | 25 +++++ tests/tcg/mips/mips32-dsp/shilov.c | 27 +++++ tests/tcg/mips/mips32-dsp/shll_ph.c | 22 ++++ tests/tcg/mips/mips32-dsp/shll_qb.c | 21 ++++ tests/tcg/mips/mips32-dsp/shll_s_ph.c | 22 ++++ tests/tcg/mips/mips32-dsp/shll_s_w.c | 22 ++++ tests/tcg/mips/mips32-dsp/shllv_ph.c | 23 ++++ tests/tcg/mips/mips32-dsp/shllv_qb.c | 22 ++++ tests/tcg/mips/mips32-dsp/shllv_s_ph.c | 23 ++++ tests/tcg/mips/mips32-dsp/shllv_s_w.c | 23 ++++ tests/tcg/mips/mips32-dsp/shra_ph.c | 18 +++ tests/tcg/mips/mips32-dsp/shra_r_ph.c | 18 +++ tests/tcg/mips/mips32-dsp/shra_r_w.c | 18 +++ tests/tcg/mips/mips32-dsp/shrav_ph.c | 19 ++++ tests/tcg/mips/mips32-dsp/shrav_r_ph.c | 19 ++++ tests/tcg/mips/mips32-dsp/shrav_r_w.c | 19 ++++ tests/tcg/mips/mips32-dsp/shrl_qb.c | 18 +++ tests/tcg/mips/mips32-dsp/shrlv_qb.c | 19 ++++ tests/tcg/mips/mips32-dsp/subq_ph.c | 23 ++++ tests/tcg/mips/mips32-dsp/subq_s_ph.c | 23 ++++ tests/tcg/mips/mips32-dsp/subq_s_w.c | 23 ++++ tests/tcg/mips/mips32-dsp/subu_qb.c | 23 ++++ tests/tcg/mips/mips32-dsp/subu_s_qb.c | 23 ++++ tests/tcg/mips/mips32-dsp/wrdsp.c | 52 +++++++++ tests/tcg/mips/mips32-dspr2/Makefile | 71 +++++++++++++ tests/tcg/mips/mips32-dspr2/absq_s_qb.c | 29 +++++ tests/tcg/mips/mips32-dspr2/addqh_ph.c | 28 +++++ tests/tcg/mips/mips32-dspr2/addqh_r_ph.c | 28 +++++ tests/tcg/mips/mips32-dspr2/addqh_r_w.c | 32 ++++++ tests/tcg/mips/mips32-dspr2/addqh_w.c | 32 ++++++ tests/tcg/mips/mips32-dspr2/addu_ph.c | 28 +++++ tests/tcg/mips/mips32-dspr2/addu_s_ph.c | 28 +++++ tests/tcg/mips/mips32-dspr2/adduh_qb.c | 28 +++++ tests/tcg/mips/mips32-dspr2/adduh_r_qb.c | 28 +++++ tests/tcg/mips/mips32-dspr2/append.c | 28 +++++ tests/tcg/mips/mips32-dspr2/balign.c | 28 +++++ tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c | 35 ++++++ tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c | 35 ++++++ tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c | 35 ++++++ tests/tcg/mips/mips32-dspr2/dpa_w_ph.c | 25 +++++ tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c | 55 ++++++++++ tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c | 28 +++++ tests/tcg/mips/mips32-dspr2/dpax_w_ph.c | 25 +++++ tests/tcg/mips/mips32-dspr2/dps_w_ph.c | 25 +++++ tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c | 29 +++++ tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c | 29 +++++ tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c | 25 +++++ tests/tcg/mips/mips32-dspr2/mul_ph.c | 23 ++++ tests/tcg/mips/mips32-dspr2/mul_s_ph.c | 23 ++++ tests/tcg/mips/mips32-dspr2/muleq_s_w_phl.c | 38 +++++++ tests/tcg/mips/mips32-dspr2/mulq_rs_w.c | 34 ++++++ tests/tcg/mips/mips32-dspr2/mulq_s_ph.c | 23 ++++ tests/tcg/mips/mips32-dspr2/mulq_s_w.c | 34 ++++++ tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c | 27 +++++ tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c | 27 +++++ tests/tcg/mips/mips32-dspr2/precr_qb_ph.c | 19 ++++ tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c | 30 ++++++ tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c | 30 ++++++ tests/tcg/mips/mips32-dspr2/prepend.c | 28 +++++ tests/tcg/mips/mips32-dspr2/shra_qb.c | 28 +++++ tests/tcg/mips/mips32-dspr2/shra_r_qb.c | 28 +++++ tests/tcg/mips/mips32-dspr2/shrav_qb.c | 30 ++++++ tests/tcg/mips/mips32-dspr2/shrav_r_qb.c | 30 ++++++ tests/tcg/mips/mips32-dspr2/shrl_ph.c | 18 +++ tests/tcg/mips/mips32-dspr2/shrlv_ph.c | 19 ++++ tests/tcg/mips/mips32-dspr2/subqh_ph.c | 19 ++++ tests/tcg/mips/mips32-dspr2/subqh_r_ph.c | 19 ++++ tests/tcg/mips/mips32-dspr2/subqh_r_w.c | 19 ++++ tests/tcg/mips/mips32-dspr2/subqh_w.c | 19 ++++ tests/tcg/mips/mips32-dspr2/subu_ph.c | 23 ++++ tests/tcg/mips/mips32-dspr2/subu_s_ph.c | 23 ++++ tests/tcg/mips/mips32-dspr2/subuh_qb.c | 19 ++++ tests/tcg/mips/mips32-dspr2/subuh_r_qb.c | 19 ++++ 160 files changed, 4282 insertions(+), 0 deletions(-) create mode 100644 tests/tcg/mips/mips32-dsp/Makefile create mode 100644 tests/tcg/mips/mips32-dsp/absq_s_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/absq_s_w.c create mode 100644 tests/tcg/mips/mips32-dsp/addq_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/addq_s_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/addsc.c create mode 100644 tests/tcg/mips/mips32-dsp/addu_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/addu_s_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/addwc.c create mode 100644 tests/tcg/mips/mips32-dsp/bitrev.c create mode 100644 tests/tcg/mips/mips32-dsp/bposge32.c create mode 100644 tests/tcg/mips/mips32-dsp/cmp_eq_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/cmp_le_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/cmp_lt_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/cmpu_le_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c create mode 100644 tests/tcg/mips/mips32-dsp/dpau_h_qbl.c create mode 100644 tests/tcg/mips/mips32-dsp/dpau_h_qbr.c create mode 100644 tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c create mode 100644 tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c create mode 100644 tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c create mode 100644 tests/tcg/mips/mips32-dsp/extp.c create mode 100644 tests/tcg/mips/mips32-dsp/extpdp.c create mode 100644 tests/tcg/mips/mips32-dsp/extpdpv.c create mode 100644 tests/tcg/mips/mips32-dsp/extpv.c create mode 100644 tests/tcg/mips/mips32-dsp/extr_r_w.c create mode 100644 tests/tcg/mips/mips32-dsp/extr_rs_w.c create mode 100644 tests/tcg/mips/mips32-dsp/extr_s_h.c create mode 100644 tests/tcg/mips/mips32-dsp/extr_w.c create mode 100644 tests/tcg/mips/mips32-dsp/extrv_r_w.c create mode 100644 tests/tcg/mips/mips32-dsp/extrv_rs_w.c create mode 100644 tests/tcg/mips/mips32-dsp/extrv_s_h.c create mode 100644 tests/tcg/mips/mips32-dsp/extrv_w.c create mode 100644 tests/tcg/mips/mips32-dsp/insv.c create mode 100644 tests/tcg/mips/mips32-dsp/lbux.c create mode 100644 tests/tcg/mips/mips32-dsp/lhx.c create mode 100644 tests/tcg/mips/mips32-dsp/lwx.c create mode 100644 tests/tcg/mips/mips32-dsp/madd.c create mode 100644 tests/tcg/mips/mips32-dsp/maddu.c create mode 100644 tests/tcg/mips/mips32-dsp/maq_s_w_phl.c create mode 100644 tests/tcg/mips/mips32-dsp/maq_s_w_phr.c create mode 100644 tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c create mode 100644 tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c create mode 100644 tests/tcg/mips/mips32-dsp/mfhi.c create mode 100644 tests/tcg/mips/mips32-dsp/mflo.c create mode 100644 tests/tcg/mips/mips32-dsp/modsub.c create mode 100644 tests/tcg/mips/mips32-dsp/msub.c create mode 100644 tests/tcg/mips/mips32-dsp/msubu.c create mode 100644 tests/tcg/mips/mips32-dsp/mthi.c create mode 100644 tests/tcg/mips/mips32-dsp/mthlip.c create mode 100644 tests/tcg/mips/mips32-dsp/mtlo.c create mode 100644 tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c create mode 100644 tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c create mode 100644 tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c create mode 100644 tests/tcg/mips/mips32-dsp/mulq_rs_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/mult.c create mode 100644 tests/tcg/mips/mips32-dsp/multu.c create mode 100644 tests/tcg/mips/mips32-dsp/packrl_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/pick_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/pick_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/preceq_w_phl.c create mode 100644 tests/tcg/mips/mips32-dsp/preceq_w_phr.c create mode 100644 tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c create mode 100644 tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c create mode 100644 tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c create mode 100644 tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c create mode 100644 tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c create mode 100644 tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c create mode 100644 tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c create mode 100644 tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c create mode 100644 tests/tcg/mips/mips32-dsp/precrq_ph_w.c create mode 100644 tests/tcg/mips/mips32-dsp/precrq_qb_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c create mode 100644 tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/raddu_w_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/rddsp.c create mode 100644 tests/tcg/mips/mips32-dsp/repl_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/repl_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/replv_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/replv_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/shilo.c create mode 100644 tests/tcg/mips/mips32-dsp/shilov.c create mode 100644 tests/tcg/mips/mips32-dsp/shll_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shll_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/shll_s_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shll_s_w.c create mode 100644 tests/tcg/mips/mips32-dsp/shllv_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shllv_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/shllv_s_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shllv_s_w.c create mode 100644 tests/tcg/mips/mips32-dsp/shra_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shra_r_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shra_r_w.c create mode 100644 tests/tcg/mips/mips32-dsp/shrav_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shrav_r_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/shrav_r_w.c create mode 100644 tests/tcg/mips/mips32-dsp/shrl_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/shrlv_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/subq_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/subq_s_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/subq_s_w.c create mode 100644 tests/tcg/mips/mips32-dsp/subu_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/subu_s_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/wrdsp.c create mode 100644 tests/tcg/mips/mips32-dspr2/Makefile create mode 100644 tests/tcg/mips/mips32-dspr2/absq_s_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/addqh_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/addqh_r_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/addqh_r_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/addqh_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/addu_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/addu_s_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/adduh_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/adduh_r_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/append.c create mode 100644 tests/tcg/mips/mips32-dspr2/balign.c create mode 100644 tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/dpa_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/dpax_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/dps_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/mul_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/mul_s_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/muleq_s_w_phl.c create mode 100644 tests/tcg/mips/mips32-dspr2/mulq_rs_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/mulq_s_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/mulq_s_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/precr_qb_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/prepend.c create mode 100644 tests/tcg/mips/mips32-dspr2/shra_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/shra_r_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/shrav_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/shrav_r_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/shrl_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/shrlv_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/subqh_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/subqh_r_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/subqh_r_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/subqh_w.c create mode 100644 tests/tcg/mips/mips32-dspr2/subu_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/subu_s_ph.c create mode 100644 tests/tcg/mips/mips32-dspr2/subuh_qb.c create mode 100644 tests/tcg/mips/mips32-dspr2/subuh_r_qb.c diff --git a/tests/tcg/mips/mips32-dsp/Makefile b/tests/tcg/mips/mips32-dsp/Makefile new file mode 100644 index 0000000..ee8a386 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/Makefile @@ -0,0 +1,133 @@ +-include ../../config-host.mak + +CROSS=mipsel-unknown-linux-gnu- + +SIM=qemu-mipsel + +CC = $(CROSS)gcc +CFLAGS = -march=mips32r2 -mgp32 -mdsp -static + +TESTCASES = absq_s_ph.tst +TESTCASES += absq_s_w.tst +TESTCASES += addq_ph.tst +TESTCASES += addq_s_ph.tst +TESTCASES += addsc.tst +TESTCASES += addu_qb.tst +TESTCASES += addu_s_qb.tst +TESTCASES += addwc.tst +TESTCASES += bitrev.tst +TESTCASES += bposge32.tst +TESTCASES += cmp_eq_ph.tst +TESTCASES += cmpgu_eq_qb.tst +TESTCASES += cmpgu_le_qb.tst +TESTCASES += cmpgu_lt_qb.tst +TESTCASES += cmp_le_ph.tst +TESTCASES += cmp_lt_ph.tst +TESTCASES += cmpu_eq_qb.tst +TESTCASES += cmpu_le_qb.tst +TESTCASES += cmpu_lt_qb.tst +TESTCASES += dpaq_sa_l_w.tst +TESTCASES += dpaq_s_w_ph.tst +TESTCASES += dpau_h_qbl.tst +TESTCASES += dpau_h_qbr.tst +TESTCASES += dpsq_sa_l_w.tst +TESTCASES += dpsq_s_w_ph.tst +TESTCASES += dpsu_h_qbl.tst +TESTCASES += dpsu_h_qbr.tst +TESTCASES += extp.tst +TESTCASES += extpdp.tst +TESTCASES += extpdpv.tst +TESTCASES += extpv.tst +TESTCASES += extr_rs_w.tst +TESTCASES += extr_r_w.tst +TESTCASES += extr_s_h.tst +TESTCASES += extrv_rs_w.tst +TESTCASES += extrv_r_w.tst +TESTCASES += extrv_s_h.tst +TESTCASES += extrv_w.tst +TESTCASES += extr_w.tst +TESTCASES += insv.tst +TESTCASES += lbux.tst +TESTCASES += lhx.tst +TESTCASES += lwx.tst +TESTCASES += madd.tst +TESTCASES += maddu.tst +TESTCASES += maq_sa_w_phl.tst +TESTCASES += maq_sa_w_phr.tst +TESTCASES += maq_s_w_phl.tst +TESTCASES += maq_s_w_phr.tst +TESTCASES += mfhi.tst +TESTCASES += mflo.tst +TESTCASES += modsub.tst +TESTCASES += msub.tst +TESTCASES += msubu.tst +TESTCASES += mthi.tst +TESTCASES += mthlip.tst +TESTCASES += mtlo.tst +TESTCASES += muleq_s_w_phr.tst +TESTCASES += muleu_s_ph_qbl.tst +TESTCASES += muleu_s_ph_qbr.tst +TESTCASES += mulq_rs_ph.tst +TESTCASES += mult.tst +TESTCASES += multu.tst +TESTCASES += packrl_ph.tst +TESTCASES += pick_ph.tst +TESTCASES += pick_qb.tst +TESTCASES += precequ_ph_qbla.tst +TESTCASES += precequ_ph_qbl.tst +TESTCASES += precequ_ph_qbra.tst +TESTCASES += precequ_ph_qbr.tst +TESTCASES += preceq_w_phl.tst +TESTCASES += preceq_w_phr.tst +TESTCASES += preceu_ph_qbla.tst +TESTCASES += preceu_ph_qbl.tst +TESTCASES += preceu_ph_qbra.tst +TESTCASES += preceu_ph_qbr.tst +TESTCASES += precrq_ph_w.tst +TESTCASES += precrq_qb_ph.tst +TESTCASES += precrq_rs_ph_w.tst +TESTCASES += precrqu_s_qb_ph.tst +TESTCASES += raddu_w_qb.tst +TESTCASES += rddsp.tst +TESTCASES += repl_ph.tst +TESTCASES += repl_qb.tst +TESTCASES += replv_ph.tst +TESTCASES += replv_qb.tst +TESTCASES += shilo.tst +TESTCASES += shilov.tst +TESTCASES += shll_ph.tst +TESTCASES += shll_qb.tst +TESTCASES += shll_s_ph.tst +TESTCASES += shll_s_w.tst +TESTCASES += shllv_ph.tst +TESTCASES += shllv_qb.tst +TESTCASES += shllv_s_ph.tst +TESTCASES += shllv_s_w.tst +TESTCASES += shra_ph.tst +TESTCASES += shra_r_ph.tst +TESTCASES += shra_r_w.tst +TESTCASES += shrav_ph.tst +TESTCASES += shrav_r_ph.tst +TESTCASES += shrav_r_w.tst +TESTCASES += shrl_qb.tst +TESTCASES += shrlv_qb.tst +TESTCASES += subq_ph.tst +TESTCASES += subq_s_ph.tst +TESTCASES += subq_s_w.tst +TESTCASES += subu_qb.tst +TESTCASES += subu_s_qb.tst +TESTCASES += wrdsp.tst + +all: $(TESTCASES) + +%.tst: %.c + $(CC) $(CFLAGS) $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) ./$$case;\ + $(SIM) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) diff --git a/tests/tcg/mips/mips32-dsp/absq_s_ph.c b/tests/tcg/mips/mips32-dsp/absq_s_ph.c new file mode 100644 index 0000000..a3e0bd7 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/absq_s_ph.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x10017EFD; + result = 0x10017EFD; + + __asm volatile + ("absq_s.ph %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); + + rt = 0x8000A536; + result = 0x7FFF5ACA; + + __asm volatile + ("absq_s.ph %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/absq_s_w.c b/tests/tcg/mips/mips32-dsp/absq_s_w.c new file mode 100644 index 0000000..e144538 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/absq_s_w.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x80000000; + result = 0x7FFFFFFF; + __asm volatile + ("absq_s.w %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); + + rt = 0x80030000; + result = 0x7FFD0000; + __asm volatile + ("absq_s.w %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); + + rt = 0x31036080; + result = 0x31036080; + __asm volatile + ("absq_s.w %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/addq_ph.c b/tests/tcg/mips/mips32-dsp/addq_ph.c new file mode 100644 index 0000000..a22f736 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addq_ph.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFFFFFFFF; + rt = 0x10101010; + result = 0x100F100F; + __asm volatile + ("addq.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x3712847D; + rt = 0x0031AF2D; + result = 0x374333AA; + __asm volatile + ("addq.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); + +} diff --git a/tests/tcg/mips/mips32-dsp/addq_s_ph.c b/tests/tcg/mips/mips32-dsp/addq_s_ph.c new file mode 100644 index 0000000..6588329 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addq_s_ph.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFFFFFFFF; + rt = 0x10101010; + result = 0x100F100F; + __asm volatile + ("addq_s.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x3712847D; + rt = 0x0031AF2D; + result = 0x37438000; + __asm volatile + ("addq_s.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); + +} diff --git a/tests/tcg/mips/mips32-dsp/addsc.c b/tests/tcg/mips/mips32-dsp/addsc.c new file mode 100644 index 0000000..93c32a3 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addsc.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x0000000F; + rt = 0x00000001; + result = 0x00000010; + __asm volatile + ("addsc %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x00001110; + __asm volatile + ("addsc %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/addu_qb.c b/tests/tcg/mips/mips32-dsp/addu_qb.c new file mode 100644 index 0000000..f72575e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addu_qb.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x00FF00FF; + rt = 0x00010001; + result = 0x00000000; + __asm volatile + ("addu.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFF011112; + __asm volatile + ("addu.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/addu_s_qb.c b/tests/tcg/mips/mips32-dsp/addu_s_qb.c new file mode 100644 index 0000000..cd1cb59 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addu_s_qb.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x10FF01FF; + rt = 0x10010001; + result = 0x20FF01FF; + __asm volatile + ("addu_s.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFFFF1112; + __asm volatile + ("addu_s.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/addwc.c b/tests/tcg/mips/mips32-dsp/addwc.c new file mode 100644 index 0000000..0ca8fd1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addwc.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x10FF01FF; + rt = 0x10010001; + result = 0x21000200; + __asm volatile + ("addwc %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0x00011112; + __asm volatile + ("addwc %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/bitrev.c b/tests/tcg/mips/mips32-dsp/bitrev.c new file mode 100644 index 0000000..fa7673a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/bitrev.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x00005678; + + __asm volatile + ("bitrev %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/bposge32.c b/tests/tcg/mips/mips32-dsp/bposge32.c new file mode 100644 index 0000000..dddc08d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/bposge32.c @@ -0,0 +1,42 @@ +#include +#include + +int main() +{ + int dsp, sum; + int result; + + dsp = 0x20; + sum = 0x01; + result = 0x02; + + __asm volatile + ("wrdsp %1\n\t" + "bposge32 test1\n\t" + "nop\n\t" + "addi %0, 0xA2 \n\t" + "nop\n\t" + "test1: \n\t" + "addi %0, 0x01 \n\t" + :"+r"(sum) + :"r"(dsp) + ); + assert(sum == result); + + dsp = 0x10; + sum = 0x01; + result = 0xA4; + + __asm volatile + ("wrdsp %1\n\t" + "bposge32 test2\n\t" + "nop\n\t" + "addi %0, 0xA2 \n\t" + "nop\n\t" + "test2: \n\t" + "addi %0, 0x01 \n\t" + :"+r"(sum) + :"r"(dsp) + ); + assert(sum == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmp_eq_ph.c b/tests/tcg/mips/mips32-dsp/cmp_eq_ph.c new file mode 100644 index 0000000..2adfc1b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmp_eq_ph.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x00; + __asm volatile + ("cmp.eq.ph %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x03; + __asm volatile + ("cmp.eq.ph %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmp_le_ph.c b/tests/tcg/mips/mips32-dsp/cmp_le_ph.c new file mode 100644 index 0000000..408cabc --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmp_le_ph.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x02; + __asm volatile + ("cmp.le.ph %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x03; + __asm volatile + ("cmp.le.ph %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmp_lt_ph.c b/tests/tcg/mips/mips32-dsp/cmp_lt_ph.c new file mode 100644 index 0000000..568a6a0 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmp_lt_ph.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x02; + __asm volatile + ("cmp.lt.ph %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm volatile + ("cmp.lt.ph %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c b/tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c new file mode 100644 index 0000000..f11017f --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm volatile + ("cmpgu.eq.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm volatile + ("cmpgu.eq.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c b/tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c new file mode 100644 index 0000000..1d30c81 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm volatile + ("cmpgu.le.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0x11777066; + rt = 0x11766066; + result = 0x09; + __asm volatile + ("cmpgu.le.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c b/tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c new file mode 100644 index 0000000..c300ed6 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm volatile + ("cmpgu.lt.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0x11777066; + rt = 0x11766066; + result = 0x00; + __asm volatile + ("cmpgu.lt.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c b/tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c new file mode 100644 index 0000000..c9d9450 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm volatile + ("cmpu.eq.qb %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm volatile + ("cmpu.eq.qb %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmpu_le_qb.c b/tests/tcg/mips/mips32-dsp/cmpu_le_qb.c new file mode 100644 index 0000000..501f77b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpu_le_qb.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm volatile + ("cmpu.le.qb %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm volatile + ("cmpu.le.qb %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); +} diff --git a/tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c b/tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c new file mode 100644 index 0000000..7e54378 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm volatile + ("cmpu.lt.qb %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm volatile + ("cmpu.lt.qb %1, %2\n\t" + "rddsp %0\n\t" + :"=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); +} diff --git a/tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c b/tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c new file mode 100644 index 0000000..14ac759 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 0, acl = 0; + int resulth, resultl, resultdsp; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x00; + resultl = 0x800003FB; + resultdsp = 0x01; + __asm volatile + ("mthi %0, $ac1 \n\t" + "mtlo %1, $ac1 \n\t" + "dpaq_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2 \n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = dsp >> 17 & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c new file mode 100644 index 0000000..470cb25 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 0, acl = 0; + int resulth, resultl, resultdsp; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x7FFFFFFF; + resultl = 0xFFFFFFFF; + resultdsp = 0x01; + __asm volatile + ("mthi %0, $ac1 \n\t" + "mtlo %0, $ac1 \n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2 \n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/dpau_h_qbl.c b/tests/tcg/mips/mips32-dsp/dpau_h_qbl.c new file mode 100644 index 0000000..0202e43 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpau_h_qbl.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 3; + int resulth, resultl; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x05; + resultl = 0x4003; + __asm volatile + ("mthi %0, $ac1 \n\t" + "mtlo %1, $ac1 \n\t" + "dpau.h.qbl $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/dpau_h_qbr.c b/tests/tcg/mips/mips32-dsp/dpau_h_qbr.c new file mode 100644 index 0000000..09fc6f1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpau_h_qbr.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 3; + int resulth, resultl; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x05; + resultl = 0x0201; + __asm volatile + ("mthi %0, $ac1 \n\t" + "mtlo %1, $ac1 \n\t" + "dpau.h.qbr $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c b/tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c new file mode 100644 index 0000000..768f06a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xEE9794A3; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c new file mode 100644 index 0000000..9a37ec8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x7FFFFFFF; + resultl = 0xFFFFFFFF; + resultdsp = 0x01; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2\n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c b/tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c new file mode 100644 index 0000000..434fc3a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFFEE5; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.qbl $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c b/tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c new file mode 100644 index 0000000..b354d6e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFE233; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.qbr $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/extp.c b/tests/tcg/mips/mips32-dsp/extp.c new file mode 100644 index 0000000..346f65d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extp.c @@ -0,0 +1,42 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + result = 0x000C; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 1); +} diff --git a/tests/tcg/mips/mips32-dsp/extpdp.c b/tests/tcg/mips/mips32-dsp/extpdp.c new file mode 100644 index 0000000..74f2efa --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extpdp.c @@ -0,0 +1,44 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp, pos, efi; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + result = 0x000C; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl) + ); + pos = dsp & 0x3F; + efi = (dsp >> 14) & 0x01; + assert(pos == 3); + assert(efi == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl) + ); + efi = (dsp >> 14) & 0x01; + assert(efi == 1); +} diff --git a/tests/tcg/mips/mips32-dsp/extpdpv.c b/tests/tcg/mips/mips32-dsp/extpdpv.c new file mode 100644 index 0000000..bdaada8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extpdpv.c @@ -0,0 +1,45 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp, pos, efi; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x000C; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl), "r"(rs) + ); + pos = dsp & 0x3F; + efi = (dsp >> 14) & 0x01; + assert(pos == 3); + assert(efi == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl), "r"(rs) + ); + efi = (dsp >> 14) & 0x01; + assert(efi == 1); +} diff --git a/tests/tcg/mips/mips32-dsp/extpv.c b/tests/tcg/mips/mips32-dsp/extpv.c new file mode 100644 index 0000000..4360429 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extpv.c @@ -0,0 +1,43 @@ +#include +#include + +int main() +{ + int rt, ac, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + ac = 0x03; + result = 0x000C; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl), "r"(ac) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(ach), "r"(acl), "r"(ac) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 1); +} diff --git a/tests/tcg/mips/mips32-dsp/extr_r_w.c b/tests/tcg/mips/mips32-dsp/extr_r_w.c new file mode 100644 index 0000000..02896a2 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_r_w.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0xA0001699; + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "=r"(dsp) + :"r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/extr_rs_w.c b/tests/tcg/mips/mips32-dsp/extr_rs_w.c new file mode 100644 index 0000000..07bf028 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_rs_w.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0x7FFFFFFF; + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_rs.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "=r"(dsp) + :"r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/extr_s_h.c b/tests/tcg/mips/mips32-dsp/extr_s_h.c new file mode 100644 index 0000000..736f6e8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_s_h.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0x00007FFF; + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_s.h %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "=r"(dsp) + :"r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/extr_w.c b/tests/tcg/mips/mips32-dsp/extr_w.c new file mode 100644 index 0000000..655f97b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_w.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0xA0001699; + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_r.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rt), "=r"(dsp) + :"r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_r_w.c b/tests/tcg/mips/mips32-dsp/extrv_r_w.c new file mode 100644 index 0000000..fadeb20 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_r_w.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0xA0001699; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_r.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_rs_w.c b/tests/tcg/mips/mips32-dsp/extrv_rs_w.c new file mode 100644 index 0000000..e27bb2a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_rs_w.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x7FFFFFFF; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_rs.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_s_h.c b/tests/tcg/mips/mips32-dsp/extrv_s_h.c new file mode 100644 index 0000000..14fa8dd --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_s_h.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x00007FFF; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_s.h %0, $ac1, %2\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_w.c b/tests/tcg/mips/mips32-dsp/extrv_w.c new file mode 100644 index 0000000..3e4a656 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_w.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0xA0001699; + + __asm volatile + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + :"=r"(rt), "+r"(dsp) + :"r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c new file mode 100644 index 0000000..65311d0 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/insv.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rt, rs, dsp; + int result; + + /* msb = 10, lsb = 5 */ + dsp = 0x305; + rt = 0x12345678; + rs = 0x87654321; + result = 0x12345338; + __asm volatile + ("wrdsp %2, 0x03\n\t" + "insv %0, %1 \n\t" + :"+r"(rt) + :"r"(rs), "r"(dsp) + ); + assert(rt == result); +} diff --git a/tests/tcg/mips/mips32-dsp/lbux.c b/tests/tcg/mips/mips32-dsp/lbux.c new file mode 100644 index 0000000..7c89374 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/lbux.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int value, index, rd; + int result; + + value = 0xBCDEF389; + index = 28; + result = value & 0xFF; + __asm volatile + ("lw $10, 28($fp)\n\t" + "sw %2, 28($fp)\n\t" + "lbux %0, %1($fp)\n\t" + "sw $10, 28($fp)\n\t" + :"=r"(rd) + :"r"(index), "r"(value) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/lhx.c b/tests/tcg/mips/mips32-dsp/lhx.c new file mode 100644 index 0000000..3341665 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/lhx.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int value, index, rd; + int result; + + value = 0xBCDEF389; + index = 28; + result = 0xFFFFF389; + __asm volatile + ("lw $10, 28($fp)\n\t" + "sw %2, 28($fp)\n\t" + "lhx %0, %1($fp)\n\t" + "sw $10, 28($fp)\n\t" + :"=r"(rd) + :"r"(index), "r"(value) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/lwx.c b/tests/tcg/mips/mips32-dsp/lwx.c new file mode 100644 index 0000000..fde8a12 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/lwx.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int value, index, rd; + int result; + + value = 0xBCDEF389; + index = 28; + result = value; + __asm volatile + ("lw $10, 28($fp)\n\t" + "sw %2, 28($fp)\n\t" + "lwx %0, %1($fp)\n\t" + "sw $10, 28($fp)\n\t" + :"=r"(rd) + :"r"(index), "r"(value) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/madd.c b/tests/tcg/mips/mips32-dsp/madd.c new file mode 100644 index 0000000..4f99446 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/madd.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x01; + rt = 0x01; + resulth = 0x05; + resultl = 0xB4CC; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "madd $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/maddu.c b/tests/tcg/mips/mips32-dsp/maddu.c new file mode 100644 index 0000000..4f99446 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maddu.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x01; + rt = 0x01; + resulth = 0x05; + resultl = 0xB4CC; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "madd $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/maq_s_w_phl.c b/tests/tcg/mips/mips32-dsp/maq_s_w_phl.c new file mode 100644 index 0000000..0e49cb0 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_s_w_phl.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF060000; + rt = 0xCB000000; + resulth = 0x04; + resultl = 0x947438CB; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.phl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/maq_s_w_phr.c b/tests/tcg/mips/mips32-dsp/maq_s_w_phr.c new file mode 100644 index 0000000..01a353b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_s_w_phr.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF06; + rt = 0xCB00; + resulth = 0x04; + resultl = 0x947438CB; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.phr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c b/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c new file mode 100644 index 0000000..a69235d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF060000; + rt = 0xCB000000; + resulth = 0xFFFFFFFF; + resultl = 0x80000000; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_sa.w.phl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c b/tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c new file mode 100644 index 0000000..aa16825 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF06; + rt = 0xCB00; + resulth = 0xFFFFFFFF; + resultl = 0x80000000; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_sa.w.phr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/mfhi.c b/tests/tcg/mips/mips32-dsp/mfhi.c new file mode 100644 index 0000000..fb836c2 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mfhi.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int achi, acho; + int result; + + achi = 0x004433; + result = 0x004433; + + __asm volatile + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + :"=r"(acho) + :"r"(achi) + ); + assert(result == acho); +} diff --git a/tests/tcg/mips/mips32-dsp/mflo.c b/tests/tcg/mips/mips32-dsp/mflo.c new file mode 100644 index 0000000..3d4b68d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mflo.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int acli, aclo; + int result; + + acli = 0x004433; + result = 0x004433; + + __asm volatile + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + :"=r"(aclo) + :"r"(acli) + ); + assert(result == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/modsub.c b/tests/tcg/mips/mips32-dsp/modsub.c new file mode 100644 index 0000000..fad018b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/modsub.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFFFFFFFF; + rt = 0x000000FF; + result = 0xFFFFFF00; + __asm volatile + ("modsub %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x00000000; + rt = 0x00CD1FFF; + result = 0x0000CD1F; + __asm volatile + ("modsub %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/msub.c b/tests/tcg/mips/mips32-dsp/msub.c new file mode 100644 index 0000000..6316249 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/msub.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int achi, acli, rs, rt; + int acho, aclo; + int resulth, resultl; + + rs = 0x00BBAACC; + rt = 0x0B1C3D2F; + achi = 0x00004433; + acli = 0xFFCC0011; + resulth = 0xFFF81F29; + resultl = 0xB355089D; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "msub $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(acho == resulth); + assert(aclo == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/msubu.c b/tests/tcg/mips/mips32-dsp/msubu.c new file mode 100644 index 0000000..85cc3f8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/msubu.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int achi, acli, rs, rt; + int acho, aclo; + int resulth, resultl; + + rs = 0x00BBAACC; + rt = 0x0B1C3D2F; + achi = 0x00004433; + acli = 0xFFCC0011; + resulth = 0xFFF81F29; + resultl = 0xB355089D; + + __asm volatile + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "msubu $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(acho), "=r"(aclo) + :"r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(acho == resulth); + assert(aclo == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/mthi.c b/tests/tcg/mips/mips32-dsp/mthi.c new file mode 100644 index 0000000..fb836c2 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mthi.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int achi, acho; + int result; + + achi = 0x004433; + result = 0x004433; + + __asm volatile + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + :"=r"(acho) + :"r"(achi) + ); + assert(result == acho); +} diff --git a/tests/tcg/mips/mips32-dsp/mthlip.c b/tests/tcg/mips/mips32-dsp/mthlip.c new file mode 100644 index 0000000..7b97442 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mthlip.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rs, ach, acl, dsp; + int result, resulth, resultl; + + dsp = 0x07; + ach = 0x05; + acl = 0xB4CB; + rs = 0x00FFBBAA; + resulth = 0xB4CB; + resultl = 0x00FFBBAA; + result = 0x27; + + __asm volatile + ("wrdsp %0, 0x01\n\t" + "mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "mthlip %3, $ac1\n\t" + "mfhi %1, $ac1\n\t" + "mflo %2, $ac1\n\t" + "rddsp %0\n\t" + :"+r"(dsp), "+r"(ach), "+r"(acl) + :"r"(rs) + ); + dsp = dsp & 0x3F; + assert(dsp == result); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/mtlo.c b/tests/tcg/mips/mips32-dsp/mtlo.c new file mode 100644 index 0000000..3d4b68d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mtlo.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int acli, aclo; + int result; + + acli = 0x004433; + result = 0x004433; + + __asm volatile + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + :"=r"(aclo) + :"r"(acli) + ); + assert(result == aclo); +} diff --git a/tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c b/tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c new file mode 100644 index 0000000..c7d54df --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c @@ -0,0 +1,38 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x8000; + rt = 0x8000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm volatile + ("muleq_s.w.phr %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x1234; + rt = 0x4321; + result = 0x98be968; + resultdsp = 1; + + __asm volatile + ("muleq_s.w.phr %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c new file mode 100644 index 0000000..b5f1796 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0xFFFF0000; + resultdsp = 1; + + __asm volatile + ("muleu_s.ph.qbl %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c new file mode 100644 index 0000000..1b01810 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x8000; + rt = 0x80004321; + result = 0xFFFF0000; + resultdsp = 1; + + __asm volatile + ("muleu_s.ph.qbr %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c new file mode 100644 index 0000000..0beb1a7 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x7FFF098C; + resultdsp = 1; + + __asm volatile + ("mulq_rs.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dsp/mult.c b/tests/tcg/mips/mips32-dsp/mult.c new file mode 100644 index 0000000..2439a1e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mult.c @@ -0,0 +1,22 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int result, resulth, resultl; + + rs = 0x00FFBBAA; + rt = 0x4B231000; + resulth = 0x4b0f01; + resultl = 0x71f8a000; + __asm volatile + ("mult $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(ach), "=r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/multu.c b/tests/tcg/mips/mips32-dsp/multu.c new file mode 100644 index 0000000..2439a1e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/multu.c @@ -0,0 +1,22 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int result, resulth, resultl; + + rs = 0x00FFBBAA; + rt = 0x4B231000; + resulth = 0x4b0f01; + resultl = 0x71f8a000; + __asm volatile + ("mult $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"=r"(ach), "=r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/packrl_ph.c b/tests/tcg/mips/mips32-dsp/packrl_ph.c new file mode 100644 index 0000000..fc9f3a8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/packrl_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x56788765; + + __asm volatile + ("packrl.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/pick_ph.c b/tests/tcg/mips/mips32-dsp/pick_ph.c new file mode 100644 index 0000000..faca7a0 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/pick_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result; + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x0A000000; + result = 0x12344321; + + __asm volatile + ("wrdsp %3, 0x10 \n\t" + "pick.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt), "r"(dsp) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/pick_qb.c b/tests/tcg/mips/mips32-dsp/pick_qb.c new file mode 100644 index 0000000..b8ea2fe --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/pick_qb.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result; + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x0A000000; + result = 0x12655621; + + __asm volatile + ("wrdsp %3, 0x10 \n\t" + "pick.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt), "r"(dsp) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/preceq_w_phl.c b/tests/tcg/mips/mips32-dsp/preceq_w_phl.c new file mode 100644 index 0000000..48b8ab8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceq_w_phl.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x87650000; + + __asm volatile + ("preceq.w.phl %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/preceq_w_phr.c b/tests/tcg/mips/mips32-dsp/preceq_w_phr.c new file mode 100644 index 0000000..6b5ccdb --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceq_w_phr.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x43210000; + + __asm volatile + ("preceq.w.phr %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c new file mode 100644 index 0000000..2520c7f --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x43803280; + + __asm volatile + ("precequ.ph.qbl %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c new file mode 100644 index 0000000..80a464b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x43802180; + + __asm volatile + ("precequ.ph.qbla %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c new file mode 100644 index 0000000..aad15de --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x21801080; + + __asm volatile + ("precequ.ph.qbr %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c new file mode 100644 index 0000000..dcd2d4a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x32801080; + + __asm volatile + ("precequ.ph.qbra %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c new file mode 100644 index 0000000..ab35646 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00870065; + + __asm volatile + ("preceu.ph.qbl %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c new file mode 100644 index 0000000..350823c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00870043; + + __asm volatile + ("preceu.ph.qbla %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c new file mode 100644 index 0000000..1956cc1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00430021; + + __asm volatile + ("preceu.ph.qbr %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c new file mode 100644 index 0000000..39ab726 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00650021; + + __asm volatile + ("preceu.ph.qbra %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precrq_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_ph_w.c new file mode 100644 index 0000000..dab6a43 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrq_ph_w.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12348765; + + __asm volatile + ("precrq.ph.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precrq_qb_ph.c b/tests/tcg/mips/mips32-dsp/precrq_qb_ph.c new file mode 100644 index 0000000..d45f5fb --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrq_qb_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12568743; + + __asm volatile + ("precrq.qb.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c new file mode 100644 index 0000000..696bc26 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12348765; + + __asm volatile + ("precrq_rs.ph.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c b/tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c new file mode 100644 index 0000000..c41f5bc --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x24AC0086; + + __asm volatile + ("precrqu_s.qb.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dsp/raddu_w_qb.c b/tests/tcg/mips/mips32-dsp/raddu_w_qb.c new file mode 100644 index 0000000..47c2598 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/raddu_w_qb.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rs; + int result; + + rs = 0x12345678; + result = 0x114; + + __asm volatile + ("raddu.w.qb %0, %1\n\t" + :"=r"(rd) + :"r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/rddsp.c b/tests/tcg/mips/mips32-dsp/rddsp.c new file mode 100644 index 0000000..0eefd89 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/rddsp.c @@ -0,0 +1,52 @@ +#include +#include + +int main() +{ + int dsp_i, dsp_o; + int ccond_i, outflag_i, efi_i, c_i, scount_i, pos_i; + int ccond_o, outflag_o, efi_o, c_o, scount_o, pos_o; + int ccond_r, outflag_r, efi_r, c_r, scount_r, pos_r; + + ccond_i = 0x000000BC;/* 4 */ + outflag_i = 0x0000001B;/* 3 */ + efi_i = 0x00000001;/* 5 */ + c_i = 0x00000001;/* 2 */ + scount_i = 0x0000000F;/* 1 */ + pos_i = 0x0000000C;/* 0 */ + + dsp_i = (ccond_i << 24) | \ + (outflag_i << 16) | \ + (efi_i << 14) | \ + (c_i << 13) | \ + (scount_i << 7 ) | \ + pos_i; + + ccond_r = ccond_i; + outflag_r = outflag_i; + efi_r = efi_i; + c_r = c_i; + scount_r = scount_i; + pos_r = pos_i; + + __asm volatile + ("wrdsp %1, 0x3F\n\t" + "rddsp %0, 0x3F\n\t" + :"=r"(dsp_o) + :"r"(dsp_i) + ); + + ccond_o = (dsp_o >> 24) & 0xFF; + outflag_o = (dsp_o >> 16) & 0xFF; + efi_o = (dsp_o >> 14) & 0x01; + c_o = (dsp_o >> 14) & 0x01; + scount_o = (dsp_o >> 7) & 0x3F; + pos_o = dsp_o & 0x1F; + + assert(ccond_o == ccond_r); + assert(outflag_o == outflag_r); + assert(efi_o == efi_r); + assert(c_o == c_r); + assert(scount_o == scount_r); + assert(pos_o == pos_r); +} diff --git a/tests/tcg/mips/mips32-dsp/repl_ph.c b/tests/tcg/mips/mips32-dsp/repl_ph.c new file mode 100644 index 0000000..0069005 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/repl_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, result; + + result = 0x01BF01BF; + __asm volatile + ("repl.ph %0, 0x1BF\n\t" + :"=r"(rd) + ); + assert(rd == result); + + result = 0xFE00FE00; + __asm volatile + ("repl.ph %0, -512\n\t" + :"=r"(rd) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/repl_qb.c b/tests/tcg/mips/mips32-dsp/repl_qb.c new file mode 100644 index 0000000..43fbfb5 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/repl_qb.c @@ -0,0 +1,14 @@ +#include +#include + +int main() +{ + int rd, result; + + result = 0xBFBFBFBF; + __asm volatile + ("repl.qb %0, 0xBF\n\t" + :"=r"(rd) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/replv_ph.c b/tests/tcg/mips/mips32-dsp/replv_ph.c new file mode 100644 index 0000000..a7f4ef5 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/replv_ph.c @@ -0,0 +1,17 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x56785678; + __asm volatile + ("replv.ph %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/replv_qb.c b/tests/tcg/mips/mips32-dsp/replv_qb.c new file mode 100644 index 0000000..f0063e8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/replv_qb.c @@ -0,0 +1,17 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x78787878; + __asm volatile + ("replv.qb %0, %1\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-dsp/shilo.c new file mode 100644 index 0000000..a3243f9 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shilo.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int ach, acl; + int resulth, resultl; + + ach = 0xBBAACCFF; + acl = 0x1C3B001D; + + resulth = 0x17755; + resultl = 0x99fe3876; + + __asm volatile + ("mthi %0, $ac1 \n\t" + "mtlo %1, $ac1 \n\t" + "shilo $ac1, 0x0F\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-dsp/shilov.c new file mode 100644 index 0000000..422fe1c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shilov.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, ach, acl; + int resulth, resultl; + + rs = 0x0F; + ach = 0xBBAACCFF; + acl = 0x1C3B001D; + + resulth = 0x17755; + resultl = 0x99fe3876; + + __asm volatile + ("mthi %0, $ac1 \n\t" + "mtlo %1, $ac1 \n\t" + "shilov $ac1, %2\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dsp/shll_ph.c b/tests/tcg/mips/mips32-dsp/shll_ph.c new file mode 100644 index 0000000..1872dae --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_ph.c @@ -0,0 +1,22 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x12345678; + result = 0xA000C000; + resultdsp = 1; + + __asm volatile + ("shll.ph %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shll_qb.c b/tests/tcg/mips/mips32-dsp/shll_qb.c new file mode 100644 index 0000000..5ff9b9e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_qb.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x87654321; + result = 0x38281808; + resultdsp = 0x01; + + __asm volatile + ("shll.qb %0, %2, 0x03\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shll_s_ph.c b/tests/tcg/mips/mips32-dsp/shll_s_ph.c new file mode 100644 index 0000000..335ddb8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_s_ph.c @@ -0,0 +1,22 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x12345678; + result = 0x7FFF7FFF; + resultdsp = 0x01; + + __asm volatile + ("shll_s.ph %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shll_s_w.c b/tests/tcg/mips/mips32-dsp/shll_s_w.c new file mode 100644 index 0000000..ac208d7 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_s_w.c @@ -0,0 +1,22 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x12345678; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm volatile + ("shll_s.w %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_ph.c b/tests/tcg/mips/mips32-dsp/shllv_ph.c new file mode 100644 index 0000000..536cf97 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x0B; + rt = 0x12345678; + result = 0xA000C000; + resultdsp = 1; + + __asm volatile + ("shllv.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_qb.c b/tests/tcg/mips/mips32-dsp/shllv_qb.c new file mode 100644 index 0000000..d22e01c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_qb.c @@ -0,0 +1,22 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x03; + rt = 0x87654321; + result = 0x38281808; + resultdsp = 0x01; + + __asm volatile + ("shllv.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_s_ph.c b/tests/tcg/mips/mips32-dsp/shllv_s_ph.c new file mode 100644 index 0000000..03958a2 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_s_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x0B; + rt = 0x12345678; + result = 0x7FFF7FFF; + resultdsp = 0x01; + + __asm volatile + ("shllv_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_s_w.c b/tests/tcg/mips/mips32-dsp/shllv_s_w.c new file mode 100644 index 0000000..8c940c1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_s_w.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x0B; + rt = 0x12345678; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm volatile + ("shllv_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shra_ph.c b/tests/tcg/mips/mips32-dsp/shra_ph.c new file mode 100644 index 0000000..4dbe547 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shra_ph.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0xF0EC0864; + + __asm volatile + ("shra.ph %0, %1, 0x03\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shra_r_ph.c b/tests/tcg/mips/mips32-dsp/shra_r_ph.c new file mode 100644 index 0000000..4d5ddc3 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shra_r_ph.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0xF0ED0864; + + __asm volatile + ("shra_r.ph %0, %1, 0x03\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shra_r_w.c b/tests/tcg/mips/mips32-dsp/shra_r_w.c new file mode 100644 index 0000000..aac78d6 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shra_r_w.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0xF0ECA864; + + __asm volatile + ("shra_r.w %0, %1, 0x03\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shrav_ph.c b/tests/tcg/mips/mips32-dsp/shrav_ph.c new file mode 100644 index 0000000..e254ff8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrav_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x87654321; + result = 0xF0EC0864; + + __asm volatile + ("shrav.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shrav_r_ph.c b/tests/tcg/mips/mips32-dsp/shrav_r_ph.c new file mode 100644 index 0000000..995b232 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrav_r_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x87654321; + result = 0xF0ED0864; + + __asm volatile + ("shrav_r.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shrav_r_w.c b/tests/tcg/mips/mips32-dsp/shrav_r_w.c new file mode 100644 index 0000000..c6dcd01 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrav_r_w.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x87654321; + result = 0xF0ECA864; + + __asm volatile + ("shrav_r.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shrl_qb.c b/tests/tcg/mips/mips32-dsp/shrl_qb.c new file mode 100644 index 0000000..d8feeca --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrl_qb.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x00010203; + + __asm volatile + ("shrl.qb %0, %1, 0x05\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/shrlv_qb.c b/tests/tcg/mips/mips32-dsp/shrlv_qb.c new file mode 100644 index 0000000..986085e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrlv_qb.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x05; + rt = 0x12345678; + result = 0x00010203; + + __asm volatile + ("shrlv.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/subq_ph.c b/tests/tcg/mips/mips32-dsp/subq_ph.c new file mode 100644 index 0000000..7def285 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subq_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x8ACF1357; + resultdsp = 0x01; + + __asm volatile + ("subq.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/subq_s_ph.c b/tests/tcg/mips/mips32-dsp/subq_s_ph.c new file mode 100644 index 0000000..e926951 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subq_s_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x7FFF1357; + resultdsp = 0x01; + + __asm volatile + ("subq_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/subq_s_w.c b/tests/tcg/mips/mips32-dsp/subq_s_w.c new file mode 100644 index 0000000..ba0d8ab --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subq_s_w.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm volatile + ("subq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/subu_qb.c b/tests/tcg/mips/mips32-dsp/subu_qb.c new file mode 100644 index 0000000..ebf1e44 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subu_qb.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x8BCF1357; + resultdsp = 0x01; + + __asm volatile + ("subu.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/subu_s_qb.c b/tests/tcg/mips/mips32-dsp/subu_s_qb.c new file mode 100644 index 0000000..f2d4388 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subu_s_qb.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x00001357; + resultdsp = 0x01; + + __asm volatile + ("subu_s.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dsp/wrdsp.c b/tests/tcg/mips/mips32-dsp/wrdsp.c new file mode 100644 index 0000000..68e849b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/wrdsp.c @@ -0,0 +1,52 @@ +#include +#include + +int main() +{ + int dsp_i, dsp_o; + int ccond_i, outflag_i, efi_i, c_i, scount_i, pos_i; + int ccond_o, outflag_o, efi_o, c_o, scount_o, pos_o; + int ccond_r, outflag_r, efi_r, c_r, scount_r, pos_r; + + ccond_i = 0x000000BC;/* 4 */ + outflag_i = 0x0000001B;/* 3 */ + efi_i = 0x00000001;/* 5 */ + c_i = 0x00000001;/* 2 */ + scount_i = 0x0000000F;/* 1 */ + pos_i = 0x0000000C;/* 0 */ + + dsp_i = (ccond_i << 24) | \ + (outflag_i << 16) | \ + (efi_i << 14) | \ + (c_i << 13) | \ + (scount_i << 7 ) | \ + pos_i; + + ccond_r = ccond_i; + outflag_r = outflag_i; + efi_r = efi_i; + c_r = c_i; + scount_r = scount_i; + pos_r = pos_i; + + __asm volatile + ("wrdsp %1, 0x3F\n\t" + "rddsp %0, 0x3F\n\t" + :"=r"(dsp_o) + :"r"(dsp_i) + ); + + ccond_o = (dsp_o >> 24) & 0xFF; + outflag_o = (dsp_o >> 16) & 0xFF; + efi_o = (dsp_o >> 14) & 0x01; + c_o = (dsp_o >> 14) & 0x01; + scount_o = (dsp_o >> 7) & 0x3F; + pos_o = dsp_o & 0x1F; + + assert(ccond_o == ccond_r); + assert(outflag_o == outflag_r); + assert(efi_o == efi_r); + assert(c_o == c_r); + assert(scount_o == scount_r); + assert(pos_o == pos_r); +} diff --git a/tests/tcg/mips/mips32-dspr2/Makefile b/tests/tcg/mips/mips32-dspr2/Makefile new file mode 100644 index 0000000..68b5649 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/Makefile @@ -0,0 +1,71 @@ +-include ../../config-host.mak + +CROSS=mipsel-unknown-linux-gnu- + +SIM=qemu-mipsel + +CC = $(CROSS)gcc +CFLAGS = -march=mips32r2 -mgp32 -mdspr2 -static + +TESTCASES = absq_s_qb.tst +TESTCASES += addqh_ph.tst +TESTCASES += addqh_r_ph.tst +TESTCASES += addqh_r_w.tst +TESTCASES += addqh_w.tst +TESTCASES += adduh_qb.tst +TESTCASES += adduh_r_qb.tst +TESTCASES += addu_ph.tst +TESTCASES += addu_s_ph.tst +TESTCASES += append.tst +TESTCASES += balign.tst +TESTCASES += cmpgdu_eq_qb.tst +TESTCASES += cmpgdu_le_qb.tst +TESTCASES += cmpgdu_lt_qb.tst +TESTCASES += dpaqx_sa_w_ph.tst +TESTCASES += dpa_w_ph.tst +TESTCASES += dpax_w_ph.tst +TESTCASES += dpaqx_s_w_ph.tst +TESTCASES += dpsqx_sa_w_ph.tst +TESTCASES += dpsqx_s_w_ph.tst +TESTCASES += dps_w_ph.tst +TESTCASES += dpsx_w_ph.tst +TESTCASES += muleq_s_w_phl.tst +TESTCASES += mul_ph.tst +TESTCASES += mulq_rs_w.tst +TESTCASES += mulq_s_ph.tst +TESTCASES += mulq_s_w.tst +TESTCASES += mulsaq_s_w_ph.tst +TESTCASES += mulsa_w_ph.tst +TESTCASES += mul_s_ph.tst +TESTCASES += precr_qb_ph.tst +TESTCASES += precr_sra_ph_w.tst +TESTCASES += precr_sra_r_ph_w.tst +TESTCASES += prepend.tst +TESTCASES += shra_qb.tst +TESTCASES += shra_r_qb.tst +TESTCASES += shrav_qb.tst +TESTCASES += shrav_r_qb.tst +TESTCASES += shrl_ph.tst +TESTCASES += shrlv_ph.tst +TESTCASES += subqh_ph.tst +TESTCASES += subqh_r_ph.tst +TESTCASES += subqh_r_w.tst +TESTCASES += subqh_w.tst +TESTCASES += subuh_qb.tst +TESTCASES += subuh_r_qb.tst +TESTCASES += subu_ph.tst +TESTCASES += subu_s_ph.tst + +all: $(TESTCASES) + +%.tst: %.c + $(CC) $(CFLAGS) $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) ./$$case;\ + $(SIM) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) diff --git a/tests/tcg/mips/mips32-dspr2/absq_s_qb.c b/tests/tcg/mips/mips32-dspr2/absq_s_qb.c new file mode 100644 index 0000000..507869f --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/absq_s_qb.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int input, result; + int hope; + + input = 0x701BA35E; + hope = 0x701B5D5E; + + __asm volatile + ("absq_s.qb %0, %1\n\t" + :"=r"(result) + :"r"(input) + ); + assert(result == hope); + + + input = 0x801BA35E; + hope = 0x7F1B5D5E; + + __asm volatile + ("absq_s.qb %0, %1\n\t" + :"=r"(result) + :"r"(input) + ); + assert(result == hope); +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_ph.c b/tests/tcg/mips/mips32-dspr2/addqh_ph.c new file mode 100644 index 0000000..10cc54c --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_ph.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x706A13FE; + rt = 0x13065174; + result = 0x41B832B9; + __asm volatile + ("addqh.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x01000100; + rt = 0x02000100; + result = 0x01800100; + __asm volatile + ("addqh.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_r_ph.c b/tests/tcg/mips/mips32-dspr2/addqh_r_ph.c new file mode 100644 index 0000000..ee8d500 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_r_ph.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x706A13FE; + rt = 0x13065174; + result = 0x41B832B9; + __asm volatile + ("addqh_r.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x01000100; + rt = 0x02000100; + result = 0x01800100; + __asm volatile + ("addqh_r.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_r_w.c b/tests/tcg/mips/mips32-dspr2/addqh_r_w.c new file mode 100644 index 0000000..19e3706 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_r_w.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x00000010; + rt = 0x00000001; + result = 0x00000009; + + __asm volatile + ("addqh_r.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0xFFFFFFFE; + rt = 0x00000001; + result = 0x00000000; + + __asm volatile + ("addqh_r.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_w.c b/tests/tcg/mips/mips32-dspr2/addqh_w.c new file mode 100644 index 0000000..1e7b86e --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_w.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x00000010; + rt = 0x00000001; + result = 0x00000008; + + __asm volatile + ("addqh.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0xFFFFFFFE; + rt = 0x00000001; + result = 0xFFFFFFFF; + + __asm volatile + ("addqh.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/addu_ph.c b/tests/tcg/mips/mips32-dspr2/addu_ph.c new file mode 100644 index 0000000..7c40478 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addu_ph.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x00FF00FF; + rt = 0x00010001; + result = 0x01000100; + __asm volatile + ("addu.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0x00011112; + __asm volatile + ("addu.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/addu_s_ph.c b/tests/tcg/mips/mips32-dspr2/addu_s_ph.c new file mode 100644 index 0000000..fb5de56 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addu_s_ph.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x00FE00FE; + rt = 0x00020001; + result = 0x010000FF; + __asm volatile + ("addu_s.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFFFF1112; + __asm volatile + ("addu_s.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/adduh_qb.c b/tests/tcg/mips/mips32-dspr2/adduh_qb.c new file mode 100644 index 0000000..c4b5c02 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/adduh_qb.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x80094B62; + __asm volatile + ("adduh.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x7F800888; + __asm volatile + ("adduh.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/adduh_r_qb.c b/tests/tcg/mips/mips32-dspr2/adduh_r_qb.c new file mode 100644 index 0000000..feee4e1 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/adduh_r_qb.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x01112211; + result = 0x80093C5E; + __asm volatile + ("adduh_r.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x80800888; + __asm volatile + ("adduh_r.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/append.c b/tests/tcg/mips/mips32-dspr2/append.c new file mode 100644 index 0000000..1d288c9 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/append.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x02268436; + __asm volatile + ("append %0, %1, 0x01\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(rt == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x0010111F; + __asm volatile + ("append %0, %1, 0x04\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(rt == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/balign.c b/tests/tcg/mips/mips32-dspr2/balign.c new file mode 100644 index 0000000..42cad83 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/balign.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x13421BFF; + __asm volatile + ("balign %0, %1, 0x01\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(rt == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x11FFFF0F; + __asm volatile + ("balign %0, %1, 0x03\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(rt == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c b/tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c new file mode 100644 index 0000000..d0c61e7 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm volatile + ("cmpgdu.eq.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm volatile + ("cmpgdu.eq.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c b/tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c new file mode 100644 index 0000000..fc16302 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm volatile + ("cmpgdu.le.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11707066; + result = 0x0B; + __asm volatile + ("cmpgdu.le.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c b/tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c new file mode 100644 index 0000000..c44f00d --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm volatile + ("cmpgdu.lt.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm volatile + ("cmpgdu.lt.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c new file mode 100644 index 0000000..7eb92c8 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x0302; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c new file mode 100644 index 0000000..07cca54 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c @@ -0,0 +1,55 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0x800000FF; + rt = 0x00018000; + resulth = 0x05; + resultl = 0x80000202; + resultdsp = 0x01; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2 \n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 5; + acl = 5; + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x05FF; + /*********************************************************** + * Because of we set outflag at last time, although this + * time we set nothing, but it is stay the last time value. + **********************************************************/ + resultdsp = 0x01; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2 \n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c new file mode 100644 index 0000000..ae3abdd --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x05FF; + resultdsp = 0x00; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2 \n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c new file mode 100644 index 0000000..1b46a3e --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x0302; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpax.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/dps_w_ph.c b/tests/tcg/mips/mips32-dspr2/dps_w_ph.c new file mode 100644 index 0000000..fed00fa --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dps_w_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x04; + resultl = 0xFFFFFD08; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dps.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c new file mode 100644 index 0000000..cf5679d --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xAEA3E09B; + resultdsp = 0x00; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2\n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c new file mode 100644 index 0000000..6ac2faf --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x00; + resultl = 0x7FFFFFFF; + resultdsp = 0x01; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + "rddsp %2\n\t" + :"+r"(ach), "+r"(acl), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c new file mode 100644 index 0000000..53e8e3e --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xD751F050; + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsx.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1 \n\t" + "mflo %1, $ac1 \n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/mul_ph.c b/tests/tcg/mips/mips32-dspr2/mul_ph.c new file mode 100644 index 0000000..197f183 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mul_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x03FB1234; + rt = 0x0BCC4321; + result = 0xF504F4B4; + resultdsp = 1; + + __asm volatile + ("mul.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dspr2/mul_s_ph.c b/tests/tcg/mips/mips32-dspr2/mul_s_ph.c new file mode 100644 index 0000000..302d30f --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mul_s_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x03FB1234; + rt = 0x0BCC4321; + result = 0x7fff7FFF; + resultdsp = 1; + + __asm volatile + ("mul_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dspr2/muleq_s_w_phl.c b/tests/tcg/mips/mips32-dspr2/muleq_s_w_phl.c new file mode 100644 index 0000000..e1bd3e8 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/muleq_s_w_phl.c @@ -0,0 +1,38 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm volatile + ("muleq_s.w.phl %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x12340000; + rt = 0x43210000; + result = 0x98be968; + resultdsp = 1; + + __asm volatile + ("muleq_s.w.phl %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dspr2/mulq_rs_w.c b/tests/tcg/mips/mips32-dspr2/mulq_rs_w.c new file mode 100644 index 0000000..73f7a9f --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulq_rs_w.c @@ -0,0 +1,34 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x80005555; + + __asm volatile + ("mulq_rs.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x80000000; + rt = 0x80000000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm volatile + ("mulq_rs.w %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dspr2/mulq_s_ph.c b/tests/tcg/mips/mips32-dspr2/mulq_s_ph.c new file mode 100644 index 0000000..b7ef6f4 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulq_s_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x7FFF098B; + resultdsp = 1; + + __asm volatile + ("mulq_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dspr2/mulq_s_w.c b/tests/tcg/mips/mips32-dspr2/mulq_s_w.c new file mode 100644 index 0000000..4539148 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulq_s_w.c @@ -0,0 +1,34 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x80005555; + + __asm volatile + ("mulq_s.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x80000000; + rt = 0x80000000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm volatile + ("mulq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); +} diff --git a/tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c b/tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c new file mode 100644 index 0000000..b7ba829 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int resulth, resultl; + + ach = 0x05; + acl = 0x00BBDDCC; + rs = 0x80001234; + rt = 0x80004321; + resulth = 0x05; + resultl = 0x3BF5E918; + + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "mulsa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c b/tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c new file mode 100644 index 0000000..9617a89 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int resulth, resultl; + + ach = 0x05; + acl = 0x00BBDDCC; + rs = 0x80001234; + rt = 0x80004321; + resulth = 0x05; + resultl = 0x772ff463; + + __asm volatile + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "mulsaq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + :"+r"(ach), "+r"(acl) + :"r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); +} diff --git a/tests/tcg/mips/mips32-dspr2/precr_qb_ph.c b/tests/tcg/mips/mips32-dspr2/precr_qb_ph.c new file mode 100644 index 0000000..9e16e9b --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/precr_qb_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x34786521; + + __asm volatile + ("precr.qb.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(result == rd); +} diff --git a/tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c b/tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c new file mode 100644 index 0000000..050a500 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x43215678; + + __asm volatile + ("precr_sra.ph.w %0, %1, 0x00\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(result == rt); + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFF0000; + + __asm volatile + ("precr_sra.ph.w %0, %1, 0x1F\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c b/tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c new file mode 100644 index 0000000..b805e73 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x43215678; + + __asm volatile + ("precr_sra_r.ph.w %0, %1, 0x00\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(result == rt); + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFF0000; + + __asm volatile + ("precr_sra_r.ph.w %0, %1, 0x1F\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(result == rt); +} diff --git a/tests/tcg/mips/mips32-dspr2/prepend.c b/tests/tcg/mips/mips32-dspr2/prepend.c new file mode 100644 index 0000000..57b18b5 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/prepend.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x87654321; + __asm volatile + ("prepend %0, %1, 0x00\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(rt == result); + + rs = 0x12345678; + rt = 0x87654321; + result = 0xACF10ECA; + __asm volatile + ("prepend %0, %1, 0x0F\n\t" + :"+r"(rt) + :"r"(rs) + ); + assert(rt == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/shra_qb.c b/tests/tcg/mips/mips32-dspr2/shra_qb.c new file mode 100644 index 0000000..6f69a7e --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shra_qb.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x02060A0F; + + __asm volatile + ("shra.qb %0, %1, 0x03\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); + + rt = 0x87654321; + result = 0xF00C0804; + + __asm volatile + ("shra.qb %0, %1, 0x03\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/shra_r_qb.c b/tests/tcg/mips/mips32-dspr2/shra_r_qb.c new file mode 100644 index 0000000..d73afbd --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shra_r_qb.c @@ -0,0 +1,28 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x02070B0F; + + __asm volatile + ("shra_r.qb %0, %1, 0x03\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); + + rt = 0x87654321; + result = 0xF10D0804; + + __asm volatile + ("shra_r.qb %0, %1, 0x03\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/shrav_qb.c b/tests/tcg/mips/mips32-dspr2/shrav_qb.c new file mode 100644 index 0000000..86bccc1 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrav_qb.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x12345678; + result = 0x02060A0F; + + __asm volatile + ("shrav.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x03; + rt = 0x87654321; + result = 0xF00C0804; + + __asm volatile + ("shrav.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/shrav_r_qb.c b/tests/tcg/mips/mips32-dspr2/shrav_r_qb.c new file mode 100644 index 0000000..ac26637 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrav_r_qb.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x12345678; + result = 0x02070B0F; + + __asm volatile + ("shrav_r.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x03; + rt = 0x87654321; + result = 0xF10D0804; + + __asm volatile + ("shrav_r.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/shrl_ph.c b/tests/tcg/mips/mips32-dspr2/shrl_ph.c new file mode 100644 index 0000000..6cd2f4f --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrl_ph.c @@ -0,0 +1,18 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x009102B3; + + __asm volatile + ("shrl.ph %0, %1, 0x05\n\t" + :"=r"(rd) + :"r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/shrlv_ph.c b/tests/tcg/mips/mips32-dspr2/shrlv_ph.c new file mode 100644 index 0000000..f16d72e --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrlv_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x05; + rt = 0x12345678; + result = 0x009102B3; + + __asm volatile + ("shrlv.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rt), "r"(rs) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_ph.c b/tests/tcg/mips/mips32-dspr2/subqh_ph.c new file mode 100644 index 0000000..4b170c3 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456709AB; + + __asm volatile + ("subqh.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_r_ph.c b/tests/tcg/mips/mips32-dspr2/subqh_r_ph.c new file mode 100644 index 0000000..d9a7578 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_r_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456809AC; + + __asm volatile + ("subqh_r.ph %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_r_w.c b/tests/tcg/mips/mips32-dspr2/subqh_r_w.c new file mode 100644 index 0000000..e038deb --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_r_w.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456789AC; + + __asm volatile + ("subqh_r.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_w.c b/tests/tcg/mips/mips32-dspr2/subqh_w.c new file mode 100644 index 0000000..872d352 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_w.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456789AB; + + __asm volatile + ("subqh.w %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subu_ph.c b/tests/tcg/mips/mips32-dspr2/subu_ph.c new file mode 100644 index 0000000..15f77c3 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subu_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x7531ECA9; + resultdsp = 0x01; + + __asm volatile + ("subu.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subu_s_ph.c b/tests/tcg/mips/mips32-dspr2/subu_s_ph.c new file mode 100644 index 0000000..e00dd8e --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subu_s_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x75310000; + resultdsp = 0x01; + + __asm volatile + ("subu_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + :"=r"(rd), "=r"(dsp) + :"r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subuh_qb.c b/tests/tcg/mips/mips32-dspr2/subuh_qb.c new file mode 100644 index 0000000..6608ce4 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subuh_qb.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xC5E7092B; + + __asm volatile + ("subuh.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} diff --git a/tests/tcg/mips/mips32-dspr2/subuh_r_qb.c b/tests/tcg/mips/mips32-dspr2/subuh_r_qb.c new file mode 100644 index 0000000..7e9dfc0 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subuh_r_qb.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xC6E80A2C; + + __asm volatile + ("subuh_r.qb %0, %1, %2\n\t" + :"=r"(rd) + :"r"(rs), "r"(rt) + ); + assert(rd == result); +} -- 1.7.5.4