From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Guan Xuetao" <gxt@mprc.pku.edu.cn>, "Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU
Date: Wed, 14 Mar 2012 02:39:54 +0100 [thread overview]
Message-ID: <1331689198-11076-4-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1331689198-11076-1-git-send-email-afaerber@suse.de>
Embed CPUUniCore32State into UniCore32CPU.
Contributed under GPLv2+.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-unicore32/cpu-qom.h | 72 ++++++++++++++++++++++++++++++++++
target-unicore32/cpu.c | 91 ++++++++++++++++++++++++++++++++++++++++++++
target-unicore32/cpu.h | 1 +
target-unicore32/helper.c | 43 +++-----------------
5 files changed, 172 insertions(+), 36 deletions(-)
create mode 100644 target-unicore32/cpu-qom.h
create mode 100644 target-unicore32/cpu.c
diff --git a/Makefile.target b/Makefile.target
index cbf62c0..7033df0 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -94,6 +94,7 @@ libobj-y += cpu_init.o
endif
libobj-$(TARGET_SPARC) += int32_helper.o
libobj-$(TARGET_SPARC64) += int64_helper.o
+libobj-$(TARGET_UNICORE32) += cpu.o
libobj-y += disas.o
libobj-$(CONFIG_TCI_DIS) += tci-dis.o
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
new file mode 100644
index 0000000..afe47e8
--- /dev/null
+++ b/target-unicore32/cpu-qom.h
@@ -0,0 +1,72 @@
+/*
+ * QEMU UniCore32 CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+#ifndef QEMU_UC32_CPU_QOM_H
+#define QEMU_UC32_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_UNICORE32_CPU "unicore32-cpu"
+
+#define UNICORE32_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(UniCore32CPUClass, (klass), TYPE_UNICORE32_CPU)
+#define UNICORE32_CPU(obj) \
+ OBJECT_CHECK(UniCore32CPU, (obj), TYPE_UNICORE32_CPU)
+#define UNICORE32_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(UniCore32CPUClass, (obj), TYPE_UNICORE32_CPU)
+
+/**
+ * UniCore32CPUClass:
+ *
+ * A UniCore32 CPU model.
+ */
+typedef struct UniCore32CPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ struct {
+ uint32_t c0_cpuid;
+ } cp0;
+} UniCore32CPUClass;
+
+/**
+ * UniCore32CPU:
+ * @env: Legacy CPU state.
+ *
+ * A UniCore32 CPU.
+ */
+typedef struct UniCore32CPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUUniCore32State env;
+} UniCore32CPU;
+
+static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
+{
+ return UNICORE32_CPU(container_of(env, UniCore32CPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
+
+
+#endif
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
new file mode 100644
index 0000000..b89a1c6
--- /dev/null
+++ b/target-unicore32/cpu.c
@@ -0,0 +1,91 @@
+/*
+ * QEMU UniCore32 CPU
+ *
+ * Copyright (c) 2010-2011 GUAN Xue-tao
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+/* CPU models */
+
+typedef struct UniCore32CPUInfo {
+ const char *name;
+ uint32_t cp0_c0_cpuid;
+} UniCore32CPUInfo;
+
+static const UniCore32CPUInfo uc32_cpus[] = {
+ {
+ .name = "UniCore-II",
+ .cp0_c0_cpuid = 0x40010863,
+ },
+ {
+ .name = "any",
+ .cp0_c0_cpuid = 0xffffffff,
+ }
+};
+
+static void uc32_cpu_initfn(Object *obj)
+{
+ UniCore32CPU *cpu = UNICORE32_CPU(obj);
+ UniCore32CPUClass *klass = UNICORE32_CPU_GET_CLASS(cpu);
+ CPUUniCore32State *env = &cpu->env;
+
+ memset(env, 0, sizeof(CPUUniCore32State));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+ env->cp0.c0_cpuid = klass->cp0.c0_cpuid;
+
+ env->uncached_asr = ASR_MODE_USER;
+ env->regs[31] = 0;
+
+ tlb_flush(env, 1);
+}
+
+static void uc32_cpu_class_init(ObjectClass *klass, void *data)
+{
+ UniCore32CPUClass *k = UNICORE32_CPU_CLASS(klass);
+ const UniCore32CPUInfo *info = data;
+
+ k->cp0.c0_cpuid = info->cp0_c0_cpuid;
+}
+
+static void uc32_register_cpu(const UniCore32CPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_UNICORE32_CPU,
+ .instance_size = sizeof(UniCore32CPU),
+ .class_size = sizeof(UniCore32CPUClass),
+ .class_init = uc32_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo uc32_cpu_info = {
+ .name = TYPE_UNICORE32_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(UniCore32CPU),
+ .instance_init = uc32_cpu_initfn,
+ .abstract = true,
+ .class_size = sizeof(UniCore32CPUClass),
+};
+
+static void uc32_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&uc32_cpu_info);
+ for (i = 0; i < ARRAY_SIZE(uc32_cpus); i++) {
+ uc32_register_cpu(&uc32_cpus[i]);
+ }
+}
+
+type_init(uc32_cpu_register_types)
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 9cbee7a..1ddd272 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -158,6 +158,7 @@ static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls)
}
#include "cpu-all.h"
+#include "cpu-qom.h"
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 6af492d..44b7842 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -16,43 +16,20 @@ static inline void set_feature(CPUUniCore32State *env, int feature)
env->features |= feature;
}
-struct uc32_cpu_t {
- uint32_t id;
- const char *name;
-};
-
-static const struct uc32_cpu_t uc32_cpu_names[] = {
- { UC32_CPUID_UCV2, "UniCore-II"},
- { UC32_CPUID_ANY, "any"},
- { 0, NULL}
-};
-
-/* return 0 if not found */
-static uint32_t uc32_cpu_find_by_name(const char *name)
-{
- int i;
- uint32_t id;
-
- id = 0;
- for (i = 0; uc32_cpu_names[i].name; i++) {
- if (strcmp(name, uc32_cpu_names[i].name) == 0) {
- id = uc32_cpu_names[i].id;
- break;
- }
- }
- return id;
-}
-
CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
+ UniCore32CPU *cpu;
CPUUniCore32State *env;
uint32_t id;
static int inited = 1;
- env = g_malloc0(sizeof(CPUUniCore32State));
- cpu_exec_init(env);
+ if (object_class_by_name(cpu_model) == NULL) {
+ return NULL;
+ }
+ cpu = UNICORE32_CPU(object_new(cpu_model));
+ env = &cpu->env;
- id = uc32_cpu_find_by_name(cpu_model);
+ id = env->cp0.c0_cpuid;
switch (id) {
case UC32_CPUID_UCV2:
set_feature(env, UC32_HWCAP_CMOV);
@@ -69,17 +46,11 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
cpu_abort(env, "Bad CPU ID: %x\n", id);
}
- env->cpu_model_str = cpu_model;
- env->cp0.c0_cpuid = id;
- env->uncached_asr = ASR_MODE_USER;
- env->regs[31] = 0;
-
if (inited) {
inited = 0;
uc32_translate_init();
}
- tlb_flush(env, 1);
qemu_init_vcpu(env);
return env;
}
--
1.7.7
next prev parent reply other threads:[~2012-03-14 1:40 UTC|newest]
Thread overview: 173+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
2012-03-05 9:23 ` Avi Kivity
2012-03-10 1:35 ` Andreas Färber
2012-03-12 10:36 ` Avi Kivity
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 2/3] qom: Register QOM infrastructure early Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators Andreas Färber
2012-03-07 14:11 ` Luiz Capitulino
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset() Andreas Färber
2012-03-13 18:02 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState Andreas Färber
2012-03-13 18:02 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions Andreas Färber
2012-03-13 18:03 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State Andreas Färber
2012-03-13 18:04 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 06/44] target-microblaze: Typedef struct CPUMBState Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 07/44] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State Andreas Färber
2012-03-13 18:05 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes Andreas Färber
2012-03-13 18:07 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState Andreas Färber
2012-03-13 18:08 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 11/44] darwin-user: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 12/44] bsd-user: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: " Andreas Färber
2012-03-13 18:10 ` Anthony Liguori
2012-03-14 20:50 ` Andreas Färber
2012-03-14 20:58 ` Peter Maydell
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 14/44] target-arm: " Andreas Färber
2012-03-14 14:39 ` Peter Maydell
2012-03-14 18:33 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 15/44] target-cris: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 16/44] target-i386: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 17/44] target-lm32: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 18/44] target-m68k: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 19/44] target-microblaze: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 20/44] target-mips: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 21/44] target-ppc: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 22/44] target-s390x: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 23/44] target-sh4: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 24/44] target-sparc: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 25/44] target-unicore32: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 26/44] target-xtensa: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 27/44] arm-semi: Don't use CPUState Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 28/44] m68k-semi: " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 29/44] xtensa-semi: " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 30/44] alpha hw/: " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 31/44] arm " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 32/44] cris " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 33/44] i386 " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 34/44] lm32 " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 35/44] m68k " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 36/44] microblaze " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 37/44] mips " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 38/44] ppc " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 39/44] s390x " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 40/44] sh4 " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 41/44] sparc " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 42/44] xtensa " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState Andreas Färber
2012-03-13 18:06 ` Andreas Färber
2012-03-13 18:11 ` Anthony Liguori
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class Andreas Färber
2012-03-12 9:38 ` Igor Mammedov
2012-03-13 12:13 ` Andreas Färber
2012-03-13 12:20 ` Paolo Bonzini
2012-03-13 12:53 ` Andreas Färber
2012-03-13 13:03 ` Paolo Bonzini
2012-03-13 18:16 ` Anthony Liguori
2012-03-14 20:37 ` Igor Mitsyanko
2012-03-14 19:48 ` Anthony Liguori
2012-03-14 19:57 ` Andreas Färber
2012-03-14 20:01 ` Anthony Liguori
2012-03-14 20:37 ` Andreas Färber
2012-03-14 20:40 ` Anthony Liguori
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list() Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass Andreas Färber
2012-03-13 12:31 ` Igor Mitsyanko
2012-03-13 17:58 ` Andreas Färber
2012-03-13 18:04 ` Eric Blake
2012-03-13 18:09 ` Eric Blake
2012-03-13 18:05 ` Paolo Bonzini
2012-03-13 18:12 ` Peter Maydell
2012-03-14 8:58 ` Igor Mitsyanko
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
2012-03-13 13:18 ` Paolo Bonzini
2012-03-14 22:30 ` Andreas Färber
2012-03-15 9:43 ` Paolo Bonzini
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 04/20] target-arm: Prepare model-specific class_init function Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState Andreas Färber
2012-03-15 18:56 ` Paul Brook
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
2012-03-15 19:08 ` Paul Brook
2012-03-15 19:20 ` Peter Maydell
2012-03-15 19:29 ` Alexey Starikovskiy
2012-03-15 19:42 ` Peter Maydell
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 11/20] target-arm: Drop JTAG_ID documentation Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 12/20] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 14/20] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 16/20] target-arm: Store CCSIDRs " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id() Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU Andreas Färber
2012-03-13 19:52 ` [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Anthony Liguori
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
2012-03-14 7:44 ` Guan Xuetao
2012-03-14 1:39 ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
2012-03-14 7:53 ` Guan Xuetao
2012-03-14 10:46 ` Andreas Färber
2012-03-14 20:03 ` Blue Swirl
2012-03-14 21:09 ` Stefan Weil
2012-03-14 21:20 ` Anthony Liguori
2012-03-14 1:39 ` Andreas Färber [this message]
2012-03-14 7:56 ` [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU Guan Xuetao
2012-03-14 10:56 ` Andreas Färber
2012-03-15 1:04 ` Guan Xuetao
2012-03-14 1:39 ` [Qemu-devel] [PATCH 4/7] target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys " Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags " Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr " Andreas Färber
2012-03-14 7:32 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Guan Xuetao
2012-03-23 16:53 ` Andreas Färber
2012-03-14 20:02 ` Blue Swirl
2012-03-14 23:23 ` Anthony Liguori
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 05/12] target-sh4: Make increment_urc() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH RFC 12/12] hw/sh7750: QOM'ify SH7750 SoC Andreas Färber
2012-03-14 16:06 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and " Peter Maydell
2012-03-14 18:25 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 03/12] target-m68k: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 04/12] target-alpha: " Andreas Färber
2012-03-14 17:59 ` Richard Henderson
2012-03-14 17:53 ` [Qemu-devel] [RFC 05/12] target-i386: " Andreas Färber
2012-03-15 19:30 ` Eduardo Habkost
2012-03-14 17:53 ` [Qemu-devel] [RFC 06/12] target-ppc: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 07/12] target-ppc: Prepare finalizer for PowerPCCPU Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 08/12] target-cris: QOM'ify CPU Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 09/12] target-lm32: " Andreas Färber
2012-03-15 22:42 ` Michael Walle
2012-03-14 17:53 ` [Qemu-devel] [RFC 10/12] target-microblaze: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 11/12] target-sparc: " Andreas Färber
2012-03-14 20:16 ` Blue Swirl
2012-03-23 17:27 ` Andreas Färber
2012-03-24 13:19 ` Blue Swirl
2012-03-14 17:53 ` [Qemu-devel] [RFC 12/12] target-xtensa: " Andreas Färber
2012-03-15 22:10 ` jcmvbkbc
2012-03-15 23:10 ` Max Filippov
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