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From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Andreas Färber" <afaerber@suse.de>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU
Date: Wed, 14 Mar 2012 17:01:29 +0100	[thread overview]
Message-ID: <1331740900-5637-2-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1331740900-5637-1-git-send-email-afaerber@suse.de>

Embed CPUSH4State into SuperHCPU. Let cpu_state_reset() call
cpu_reset(). Let sh4_cpu_list() enumerate CPU classes alphabetically.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 Makefile.target        |    1 +
 target-sh4/cpu-qom.h   |   78 +++++++++++++++++++++++
 target-sh4/cpu.c       |  161 ++++++++++++++++++++++++++++++++++++++++++++++++
 target-sh4/cpu.h       |    1 +
 target-sh4/translate.c |  119 +++++++++++------------------------
 5 files changed, 278 insertions(+), 82 deletions(-)
 create mode 100644 target-sh4/cpu-qom.h
 create mode 100644 target-sh4/cpu.c

diff --git a/Makefile.target b/Makefile.target
index 7033df0..c48a849 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -88,6 +88,7 @@ libobj-$(TARGET_SPARC64) += vis_helper.o
 libobj-$(CONFIG_NEED_MMU) += mmu.o
 libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
 libobj-$(TARGET_ARM) += cpu.o
+libobj-$(TARGET_SH4) += cpu.o
 ifeq ($(TARGET_BASE_ARCH), sparc)
 libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
 libobj-y += cpu_init.o
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
new file mode 100644
index 0000000..1441328
--- /dev/null
+++ b/target-sh4/cpu-qom.h
@@ -0,0 +1,78 @@
+/*
+ * QEMU SuperH CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_SUPERH_CPU_QOM_H
+#define QEMU_SUPERH_CPU_QOM_H
+
+#include "qemu-common.h"
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_SUPERH_CPU "superh-cpu"
+
+#define SUPERH_CPU_CLASS(klass) \
+    OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
+#define SUPERH_CPU(obj) \
+    OBJECT_CHECK(SuperHCPU, (obj), TYPE_SUPERH_CPU)
+#define SUPERH_CPU_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(SuperHCPUClass, (obj), TYPE_SUPERH_CPU)
+
+/**
+ * SuperHCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A SuperH CPU model.
+ */
+typedef struct SuperHCPUClass {
+    /*< private >*/
+    CPUClass parent_class;
+    /*< public >*/
+
+    void (*parent_reset)(CPUState *cpu);
+
+    int id;
+    uint32_t pvr;
+    uint32_t prr;
+    uint32_t cvr;
+    uint32_t features;
+} SuperHCPUClass;
+
+/**
+ * SuperHCPU:
+ * @env: Legacy CPU state.
+ *
+ * A SuperH CPU.
+ */
+typedef struct SuperHCPU {
+    /*< private >*/
+    CPUState parent_obj;
+    /*< public >*/
+
+    CPUSH4State env;
+} SuperHCPU;
+
+static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
+{
+    return SUPERH_CPU(container_of(env, SuperHCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e))
+
+
+#endif
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
new file mode 100644
index 0000000..68034b6
--- /dev/null
+++ b/target-sh4/cpu.c
@@ -0,0 +1,161 @@
+/*
+ * QEMU SuperH CPU
+ *
+ * Copyright (c) 2005 Samuel Tardieu
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void superh_cpu_reset(CPUState *c)
+{
+    SuperHCPU *cpu = SUPERH_CPU(c);
+    SuperHCPUClass *klass = SUPERH_CPU_GET_CLASS(cpu);
+    CPUSH4State *env = &cpu->env;
+
+    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+        qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+        log_cpu_state(env, 0);
+    }
+
+    klass->parent_reset(c);
+
+    memset(env, 0, offsetof(CPUSH4State, breakpoints));
+    tlb_flush(env, 1);
+
+    env->pc = 0xA0000000;
+#if defined(CONFIG_USER_ONLY)
+    env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
+    set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
+#else
+    env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
+    env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to
+                                              SH4 manual */
+    set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+    set_flush_to_zero(1, &env->fp_status);
+#endif
+    set_default_nan_mode(1, &env->fp_status);
+}
+
+/* CPU models */
+
+typedef struct {
+    const char *name;
+    int id;
+    uint32_t pvr;
+    uint32_t prr;
+    uint32_t cvr;
+    uint32_t features;
+} SuperHCPUInfo;
+
+static const SuperHCPUInfo superh_cpus[] = {
+    {
+        .name = "SH7750R",
+        .id = SH_CPU_SH7750R,
+        .pvr = 0x00050000,
+        .prr = 0x00000100,
+        .cvr = 0x00110000,
+        .features = SH_FEATURE_BCR3_AND_BCR4,
+    }, {
+        .name = "SH7751R",
+        .id = SH_CPU_SH7751R,
+        .pvr = 0x04050005,
+        .prr = 0x00000113,
+        .cvr = 0x00110000,    /* Neutered caches, should be 0x20480000 */
+        .features = SH_FEATURE_BCR3_AND_BCR4,
+    }, {
+        .name = "SH7785",
+        .id = SH_CPU_SH7785,
+        .pvr = 0x10300700,
+        .prr = 0x00000200,
+        .cvr = 0x71440211,
+        .features = SH_FEATURE_SH4A,
+    },
+};
+
+static void superh_cpu_initfn(Object *obj)
+{
+    SuperHCPU *cpu = SUPERH_CPU(obj);
+    SuperHCPUClass *klass = SUPERH_CPU_GET_CLASS(cpu);
+    CPUSH4State *env = &cpu->env;
+
+    memset(env, 0, sizeof(CPUSH4State));
+    env->cpu_model_str = object_get_typename(obj);
+    cpu_exec_init(env);
+
+    env->id = klass->id;
+    env->pvr = klass->pvr;
+    env->prr = klass->prr;
+    env->cvr = klass->cvr;
+    env->features = klass->features;
+
+    env->movcal_backup_tail = &(env->movcal_backup);
+
+    cpu_reset(CPU(cpu));
+}
+
+static void superh_cpu_class_init(ObjectClass *klass, void *data)
+{
+    CPUClass *cpu_class = CPU_CLASS(klass);
+    SuperHCPUClass *k = SUPERH_CPU_CLASS(klass);
+    const SuperHCPUInfo *info = data;
+
+    k->parent_reset = cpu_class->reset;
+    cpu_class->reset = superh_cpu_reset;
+
+    k->id = info->id;
+    k->pvr = info->pvr;
+    k->prr = info->prr;
+    k->cvr = info->cvr;
+    k->features = info->features;
+}
+
+static void cpu_register(const SuperHCPUInfo *info)
+{
+    TypeInfo type = {
+        .name = info->name,
+        .parent = TYPE_SUPERH_CPU,
+        .instance_size = sizeof(SuperHCPU),
+        .instance_init = superh_cpu_initfn,
+        .class_size = sizeof(SuperHCPUClass),
+        .class_init = superh_cpu_class_init,
+        .class_data = (void *)info,
+    };
+
+    type_register_static(&type);
+}
+
+static const TypeInfo superh_cpu_type_info = {
+    .name = TYPE_SUPERH_CPU,
+    .parent = TYPE_CPU,
+    .instance_size = sizeof(SuperHCPU),
+    .abstract = true,
+    .class_size = sizeof(SuperHCPUClass),
+};
+
+static void superh_cpu_register_types(void)
+{
+    int i;
+
+    type_register_static(&superh_cpu_type_info);
+    for (i = 0; i < ARRAY_SIZE(superh_cpus); i++) {
+        cpu_register(&superh_cpus[i]);
+    }
+}
+
+type_init(superh_cpu_register_types)
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 965536d..ec5e6cf 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -255,6 +255,7 @@ static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp)
 #endif
 
 #include "cpu-all.h"
+#include "cpu-qom.h"
 
 /* Memory access type */
 enum {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index a337beb..71434d0 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -180,107 +180,62 @@ void cpu_dump_state(CPUSH4State * env, FILE * f,
 
 void cpu_state_reset(CPUSH4State *env)
 {
-    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
-        qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
-        log_cpu_state(env, 0);
-    }
-
-    memset(env, 0, offsetof(CPUSH4State, breakpoints));
-    tlb_flush(env, 1);
-
-    env->pc = 0xA0000000;
-#if defined(CONFIG_USER_ONLY)
-    env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
-    set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
-#else
-    env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
-    env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
-    set_float_rounding_mode(float_round_to_zero, &env->fp_status);
-    set_flush_to_zero(1, &env->fp_status);
-#endif
-    set_default_nan_mode(1, &env->fp_status);
+    cpu_reset(ENV_GET_CPU(env));
 }
 
-typedef struct {
-    const char *name;
-    int id;
-    uint32_t pvr;
-    uint32_t prr;
-    uint32_t cvr;
-    uint32_t features;
-} sh4_def_t;
-
-static sh4_def_t sh4_defs[] = {
-    {
-	.name = "SH7750R",
-	.id = SH_CPU_SH7750R,
-	.pvr = 0x00050000,
-	.prr = 0x00000100,
-	.cvr = 0x00110000,
-	.features = SH_FEATURE_BCR3_AND_BCR4,
-    }, {
-	.name = "SH7751R",
-	.id = SH_CPU_SH7751R,
-	.pvr = 0x04050005,
-	.prr = 0x00000113,
-	.cvr = 0x00110000,	/* Neutered caches, should be 0x20480000 */
-	.features = SH_FEATURE_BCR3_AND_BCR4,
-    }, {
-	.name = "SH7785",
-	.id = SH_CPU_SH7785,
-	.pvr = 0x10300700,
-	.prr = 0x00000200,
-	.cvr = 0x71440211,
-	.features = SH_FEATURE_SH4A,
-     },
-};
+typedef struct SuperHCPUListState {
+    fprintf_function cpu_fprintf;
+    FILE *file;
+} SuperHCPUListState;
 
-static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
+static gint sh_cpu_list_compare(gconstpointer a, gconstpointer b)
 {
-    int i;
-
-    if (strcasecmp(name, "any") == 0)
-	return &sh4_defs[0];
+    ObjectClass *class_a = (ObjectClass *)a;
+    ObjectClass *class_b = (ObjectClass *)b;
 
-    for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
-	if (strcasecmp(name, sh4_defs[i].name) == 0)
-	    return &sh4_defs[i];
-
-    return NULL;
+    return strcasecmp(object_class_get_name(class_a),
+                      object_class_get_name(class_b));
 }
 
-void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+static void sh_cpu_list_entry(gpointer data, gpointer user_data)
 {
-    int i;
+    ObjectClass *klass = data;
+    SuperHCPUListState *s = user_data;
 
-    for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
-	(*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
+    (*s->cpu_fprintf)(s->file, "%s\n",
+                      object_class_get_name(klass));
 }
 
-static void cpu_register(CPUSH4State *env, const sh4_def_t *def)
+void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 {
-    env->pvr = def->pvr;
-    env->prr = def->prr;
-    env->cvr = def->cvr;
-    env->id = def->id;
+    SuperHCPUListState s = {
+        .cpu_fprintf = cpu_fprintf,
+        .file = f,
+    };
+    GSList *list;
+
+    list = object_class_get_list(TYPE_SUPERH_CPU, false);
+    list = g_slist_sort(list, sh_cpu_list_compare);
+    g_slist_foreach(list, sh_cpu_list_entry, &s);
+    g_slist_free(list);
 }
 
 CPUSH4State *cpu_sh4_init(const char *cpu_model)
 {
+    SuperHCPU *cpu;
     CPUSH4State *env;
-    const sh4_def_t *def;
 
-    def = cpu_sh4_find_by_name(cpu_model);
-    if (!def)
-	return NULL;
-    env = g_malloc0(sizeof(CPUSH4State));
-    env->features = def->features;
-    cpu_exec_init(env);
-    env->movcal_backup_tail = &(env->movcal_backup);
+    if (strcasecmp(cpu_model, "any") == 0) {
+        cpu_model = "SH7750R";
+    }
+    if (object_class_by_name(cpu_model) == NULL) {
+        return NULL;
+    }
+    cpu = SUPERH_CPU(object_new(cpu_model));
+    env = &cpu->env;
+
     sh4_translate_init();
-    env->cpu_model_str = cpu_model;
-    cpu_state_reset(env);
-    cpu_register(env, def);
+
     qemu_init_vcpu(env);
     return env;
 }
-- 
1.7.7

  reply	other threads:[~2012-03-14 16:02 UTC|newest]

Thread overview: 173+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
2012-03-05  9:23   ` Avi Kivity
2012-03-10  1:35     ` Andreas Färber
2012-03-12 10:36       ` Avi Kivity
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 2/3] qom: Register QOM infrastructure early Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators Andreas Färber
2012-03-07 14:11   ` Luiz Capitulino
2012-03-10  2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset() Andreas Färber
2012-03-13 18:02     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState Andreas Färber
2012-03-13 18:02     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions Andreas Färber
2012-03-13 18:03     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State Andreas Färber
2012-03-13 18:04     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 06/44] target-microblaze: Typedef struct CPUMBState Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 07/44] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State Andreas Färber
2012-03-13 18:05     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes Andreas Färber
2012-03-13 18:07     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState Andreas Färber
2012-03-13 18:08     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 11/44] darwin-user: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 12/44] bsd-user: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: " Andreas Färber
2012-03-13 18:10     ` Anthony Liguori
2012-03-14 20:50       ` Andreas Färber
2012-03-14 20:58         ` Peter Maydell
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 14/44] target-arm: " Andreas Färber
2012-03-14 14:39     ` Peter Maydell
2012-03-14 18:33       ` Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 15/44] target-cris: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 16/44] target-i386: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 17/44] target-lm32: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 18/44] target-m68k: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 19/44] target-microblaze: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 20/44] target-mips: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 21/44] target-ppc: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 22/44] target-s390x: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 23/44] target-sh4: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 24/44] target-sparc: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 25/44] target-unicore32: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 26/44] target-xtensa: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 27/44] arm-semi: Don't use CPUState Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 28/44] m68k-semi: " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 29/44] xtensa-semi: " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 30/44] alpha hw/: " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 31/44] arm " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 32/44] cris " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 33/44] i386 " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 34/44] lm32 " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 35/44] m68k " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 36/44] microblaze " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 37/44] mips " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 38/44] ppc " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 39/44] s390x " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 40/44] sh4 " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 41/44] sparc " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 42/44] xtensa " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState Andreas Färber
2012-03-13 18:06     ` Andreas Färber
2012-03-13 18:11       ` Anthony Liguori
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class Andreas Färber
2012-03-12  9:38     ` Igor Mammedov
2012-03-13 12:13       ` Andreas Färber
2012-03-13 12:20         ` Paolo Bonzini
2012-03-13 12:53           ` Andreas Färber
2012-03-13 13:03             ` Paolo Bonzini
2012-03-13 18:16           ` Anthony Liguori
2012-03-14 20:37         ` Igor Mitsyanko
2012-03-14 19:48           ` Anthony Liguori
2012-03-14 19:57             ` Andreas Färber
2012-03-14 20:01               ` Anthony Liguori
2012-03-14 20:37           ` Andreas Färber
2012-03-14 20:40             ` Anthony Liguori
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list() Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass Andreas Färber
2012-03-13 12:31     ` Igor Mitsyanko
2012-03-13 17:58       ` Andreas Färber
2012-03-13 18:04         ` Eric Blake
2012-03-13 18:09           ` Eric Blake
2012-03-13 18:05         ` Paolo Bonzini
2012-03-13 18:12         ` Peter Maydell
2012-03-14  8:58         ` Igor Mitsyanko
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
2012-03-13 13:18     ` Paolo Bonzini
2012-03-14 22:30       ` Andreas Färber
2012-03-15  9:43         ` Paolo Bonzini
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 04/20] target-arm: Prepare model-specific class_init function Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState Andreas Färber
2012-03-15 18:56     ` Paul Brook
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
2012-03-15 19:08     ` Paul Brook
2012-03-15 19:20       ` Peter Maydell
2012-03-15 19:29         ` Alexey Starikovskiy
2012-03-15 19:42           ` Peter Maydell
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 11/20] target-arm: Drop JTAG_ID documentation Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 12/20] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 14/20] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 16/20] target-arm: Store CCSIDRs " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id() Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU Andreas Färber
2012-03-13 19:52 ` [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Anthony Liguori
2012-03-14  1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
2012-03-14  7:44     ` Guan Xuetao
2012-03-14  1:39   ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
2012-03-14  7:53     ` Guan Xuetao
2012-03-14 10:46       ` Andreas Färber
2012-03-14 20:03     ` Blue Swirl
2012-03-14 21:09     ` Stefan Weil
2012-03-14 21:20       ` Anthony Liguori
2012-03-14  1:39   ` [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU Andreas Färber
2012-03-14  7:56     ` Guan Xuetao
2012-03-14 10:56       ` Andreas Färber
2012-03-15  1:04         ` Guan Xuetao
2012-03-14  1:39   ` [Qemu-devel] [PATCH 4/7] target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys " Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags " Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr " Andreas Färber
2012-03-14  7:32   ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Guan Xuetao
2012-03-23 16:53     ` Andreas Färber
2012-03-14 20:02   ` Blue Swirl
2012-03-14 23:23     ` Anthony Liguori
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
2012-03-14 16:01   ` Andreas Färber [this message]
2012-03-14 16:01   ` [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 05/12] target-sh4: Make increment_urc() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH RFC 12/12] hw/sh7750: QOM'ify SH7750 SoC Andreas Färber
2012-03-14 16:06   ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and " Peter Maydell
2012-03-14 18:25     ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 03/12] target-m68k: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 04/12] target-alpha: " Andreas Färber
2012-03-14 17:59     ` Richard Henderson
2012-03-14 17:53   ` [Qemu-devel] [RFC 05/12] target-i386: " Andreas Färber
2012-03-15 19:30     ` Eduardo Habkost
2012-03-14 17:53   ` [Qemu-devel] [RFC 06/12] target-ppc: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 07/12] target-ppc: Prepare finalizer for PowerPCCPU Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 08/12] target-cris: QOM'ify CPU Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 09/12] target-lm32: " Andreas Färber
2012-03-15 22:42     ` Michael Walle
2012-03-14 17:53   ` [Qemu-devel] [RFC 10/12] target-microblaze: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 11/12] target-sparc: " Andreas Färber
2012-03-14 20:16     ` Blue Swirl
2012-03-23 17:27       ` Andreas Färber
2012-03-24 13:19         ` Blue Swirl
2012-03-14 17:53   ` [Qemu-devel] [RFC 12/12] target-xtensa: " Andreas Färber
2012-03-15 22:10     ` jcmvbkbc
2012-03-15 23:10       ` Max Filippov

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