From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38962) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qeb-0004ob-EH for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7qe6-0002Ce-Qd for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:21 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44480 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qe6-0002Bg-EQ for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:01:50 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 14 Mar 2012 17:01:35 +0100 Message-Id: <1331740900-5637-8-git-send-email-afaerber@suse.de> In-Reply-To: <1331740900-5637-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331740900-5637-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Change argument type to SuperHCPU and update the SH7750 SoC. Signed-off-by: Andreas F=C3=A4rber --- hw/sh7750.c | 16 ++++++------ target-sh4/cpu.h | 16 ++++++------ target-sh4/helper.c | 63 ++++++++++++++++++++++++++-------------------= ------ 3 files changed, 48 insertions(+), 47 deletions(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index ca7839e..c3cea9f 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -649,20 +649,20 @@ static uint64_t sh7750_mmct_read(void *opaque, targ= et_phys_addr_t addr, /* do nothing */ break; case MM_ITLB_ADDR: - ret =3D cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); + ret =3D cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); break; case MM_ITLB_DATA: - ret =3D cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); + ret =3D cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: - ret =3D cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); + ret =3D cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); break; case MM_UTLB_DATA: - ret =3D cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); + ret =3D cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); break; default: abort(); @@ -692,10 +692,10 @@ static void sh7750_mmct_write(void *opaque, target_= phys_addr_t addr, /* do nothing */ break; case MM_ITLB_ADDR: - cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); + cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); break; case MM_ITLB_DATA: - cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); + cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); abort(); break; case MM_OCACHE_ADDR: @@ -703,10 +703,10 @@ static void sh7750_mmct_write(void *opaque, target_= phys_addr_t addr, /* do nothing */ break; case MM_UTLB_ADDR: - cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); + cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); break; case MM_UTLB_DATA: - cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); + cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); break; default: abort(); diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 32e59e7..b3abece 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -200,21 +200,21 @@ void do_interrupt(CPUSH4State * env); void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); #if !defined(CONFIG_USER_ONLY) void cpu_sh4_invalidate_tlb(SuperHCPU *cpu); -uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_itlb_addr(SuperHCPU *cpu, target_phys_addr_t addr); -void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_itlb_addr(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value); -uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_itlb_data(SuperHCPU *cpu, target_phys_addr_t addr); -void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_itlb_data(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value); -uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_utlb_addr(SuperHCPU *cpu, target_phys_addr_t addr); -void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_utlb_addr(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value); -uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_utlb_data(SuperHCPU *cpu, target_phys_addr_t addr); -void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_utlb_data(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value); #endif =20 diff --git a/target-sh4/helper.c b/target-sh4/helper.c index d2186ed..3653ece 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -574,18 +574,18 @@ void cpu_sh4_invalidate_tlb(SuperHCPU *cpu) tlb_flush(&cpu->env, 1); } =20 -uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_itlb_addr(SuperHCPU *cpu, target_phys_addr_t addr) { int index =3D (addr & 0x00000300) >> 8; - tlb_t * entry =3D &s->itlb[index]; + tlb_t *entry =3D &cpu->env.itlb[index]; =20 return (entry->vpn << 10) | (entry->v << 8) | (entry->asid); } =20 -void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_itlb_addr(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value) { uint32_t vpn =3D (mem_value & 0xfffffc00) >> 10; @@ -593,23 +593,23 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s,= target_phys_addr_t addr, uint8_t asid =3D (uint8_t)(mem_value & 0x000000ff); =20 int index =3D (addr & 0x00000300) >> 8; - tlb_t * entry =3D &s->itlb[index]; + tlb_t *entry =3D &cpu->env.itlb[index]; if (entry->v) { /* Overwriting valid entry in itlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(&cpu->env, address); } entry->asid =3D asid; entry->vpn =3D vpn; entry->v =3D v; } =20 -uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_itlb_data(SuperHCPU *cpu, target_phys_addr_t addr) { int array =3D (addr & 0x00800000) >> 23; int index =3D (addr & 0x00000300) >> 8; - tlb_t * entry =3D &s->itlb[index]; + tlb_t *entry =3D &cpu->env.itlb[index]; =20 if (array =3D=3D 0) { /* ITLB Data Array 1 */ @@ -627,19 +627,19 @@ uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State = *s, } } =20 -void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_itlb_data(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value) { int array =3D (addr & 0x00800000) >> 23; int index =3D (addr & 0x00000300) >> 8; - tlb_t * entry =3D &s->itlb[index]; + tlb_t *entry =3D &cpu->env.itlb[index]; =20 if (array =3D=3D 0) { /* ITLB Data Array 1 */ if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(&cpu->env, address); } entry->ppn =3D (mem_value & 0x1ffffc00) >> 10; entry->v =3D (mem_value & 0x00000100) >> 8; @@ -655,20 +655,20 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s,= target_phys_addr_t addr, } } =20 -uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_utlb_addr(SuperHCPU *cpu, target_phys_addr_t addr) { int index =3D (addr & 0x00003f00) >> 8; - tlb_t * entry =3D &s->utlb[index]; + tlb_t *entry =3D &cpu->env.utlb[index]; =20 - increment_urc(sh_env_get_cpu(s)); /* per utlb access */ + increment_urc(cpu); /* per utlb access */ =20 return (entry->vpn << 10) | (entry->v << 8) | (entry->asid); } =20 -void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_utlb_addr(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value) { int associate =3D addr & 0x0000080; @@ -676,7 +676,8 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, t= arget_phys_addr_t addr, uint8_t d =3D (uint8_t)((mem_value & 0x00000200) >> 9); uint8_t v =3D (uint8_t)((mem_value & 0x00000100) >> 8); uint8_t asid =3D (uint8_t)(mem_value & 0x000000ff); - int use_asid =3D (s->mmucr & MMUCR_SV) =3D=3D 0 || (s->sr & SR_MD) =3D= =3D 0; + int use_asid =3D (cpu->env.mmucr & MMUCR_SV) =3D=3D 0 || + (cpu->env.sr & SR_MD) =3D=3D 0; =20 if (associate) { int i; @@ -685,7 +686,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, t= arget_phys_addr_t addr, =20 /* search UTLB */ for (i =3D 0; i < UTLB_SIZE; i++) { - tlb_t * entry =3D &s->utlb[i]; + tlb_t *entry =3D &cpu->env.utlb[i]; if (!entry->v) continue; =20 @@ -693,8 +694,8 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, t= arget_phys_addr_t addr, && (!use_asid || entry->asid =3D=3D asid || entry->sh)) = { if (utlb_match_entry) { /* Multiple TLB Exception */ - s->exception_index =3D 0x140; - s->tea =3D addr; + cpu->env.exception_index =3D 0x140; + cpu->env.tea =3D addr; break; } if (entry->v && !v) @@ -703,12 +704,12 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s,= target_phys_addr_t addr, entry->d =3D d; utlb_match_entry =3D entry; } - increment_urc(sh_env_get_cpu(s)); /* per utlb access */ + increment_urc(cpu); /* per utlb access */ } =20 /* search ITLB */ for (i =3D 0; i < ITLB_SIZE; i++) { - tlb_t * entry =3D &s->itlb[i]; + tlb_t *entry =3D &cpu->env.itlb[i]; if (entry->vpn =3D=3D vpn && (!use_asid || entry->asid =3D=3D asid || entry->sh)) = { if (entry->v && !v) @@ -722,32 +723,32 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s,= target_phys_addr_t addr, } =20 if (needs_tlb_flush) - tlb_flush_page(s, vpn << 10); + tlb_flush_page(&cpu->env, vpn << 10); =20 } else { int index =3D (addr & 0x00003f00) >> 8; - tlb_t * entry =3D &s->utlb[index]; + tlb_t *entry =3D &cpu->env.utlb[index]; if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(&cpu->env, address); } entry->asid =3D asid; entry->vpn =3D vpn; entry->d =3D d; entry->v =3D v; - increment_urc(sh_env_get_cpu(s)); + increment_urc(cpu); } } =20 -uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, +uint32_t cpu_sh4_read_mmaped_utlb_data(SuperHCPU *cpu, target_phys_addr_t addr) { int array =3D (addr & 0x00800000) >> 23; int index =3D (addr & 0x00003f00) >> 8; - tlb_t * entry =3D &s->utlb[index]; + tlb_t *entry =3D &cpu->env.utlb[index]; =20 - increment_urc(sh_env_get_cpu(s)); /* per utlb access */ + increment_urc(cpu); /* per utlb access */ =20 if (array =3D=3D 0) { /* ITLB Data Array 1 */ @@ -767,21 +768,21 @@ uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State = *s, } } =20 -void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t a= ddr, +void cpu_sh4_write_mmaped_utlb_data(SuperHCPU *cpu, target_phys_addr_t a= ddr, uint32_t mem_value) { int array =3D (addr & 0x00800000) >> 23; int index =3D (addr & 0x00003f00) >> 8; - tlb_t * entry =3D &s->utlb[index]; + tlb_t *entry =3D &cpu->env.utlb[index]; =20 - increment_urc(sh_env_get_cpu(s)); /* per utlb access */ + increment_urc(cpu); /* per utlb access */ =20 if (array =3D=3D 0) { /* UTLB Data Array 1 */ if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(&cpu->env, address); } entry->ppn =3D (mem_value & 0x1ffffc00) >> 10; entry->v =3D (mem_value & 0x00000100) >> 8; --=20 1.7.7