qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [RFC 08/12] target-cris: QOM'ify CPU
Date: Wed, 14 Mar 2012 18:53:32 +0100	[thread overview]
Message-ID: <1331747617-7837-9-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1331747617-7837-1-git-send-email-afaerber@suse.de>

Let cris_cpu_list() enumerate CPU classes sorted by version.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 Makefile.target         |    1 +
 target-cris/cpu-qom.h   |   73 ++++++++++++++++++++++++
 target-cris/cpu.c       |  144 +++++++++++++++++++++++++++++++++++++++++++++++
 target-cris/cpu.h       |    2 +
 target-cris/translate.c |   93 ++++++++++++++----------------
 5 files changed, 264 insertions(+), 49 deletions(-)
 create mode 100644 target-cris/cpu-qom.h
 create mode 100644 target-cris/cpu.c

diff --git a/Makefile.target b/Makefile.target
index c655091..3b7a4da 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -89,6 +89,7 @@ libobj-$(CONFIG_NEED_MMU) += mmu.o
 libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
 libobj-$(TARGET_ALPHA) += cpu.o
 libobj-$(TARGET_ARM) += cpu.o
+libobj-$(TARGET_CRIS) += cpu.o
 libobj-$(TARGET_M68K) += cpu.o
 ifeq ($(TARGET_BASE_ARCH), mips)
 libobj-y += cpu.o
diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h
new file mode 100644
index 0000000..bbd0c71
--- /dev/null
+++ b/target-cris/cpu-qom.h
@@ -0,0 +1,73 @@
+/*
+ * QEMU CRIS CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_CRIS_CPU_QOM_H
+#define QEMU_CRIS_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_CRIS_CPU "cris-cpu"
+
+#define CRIS_CPU_CLASS(klass) \
+    OBJECT_CLASS_CHECK(CRISCPUClass, (klass), TYPE_CRIS_CPU)
+#define CRIS_CPU(obj) \
+    OBJECT_CHECK(CRISCPU, (obj), TYPE_CRIS_CPU)
+#define CRIS_CPU_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(CRISCPUClass, (obj), TYPE_CRIS_CPU)
+
+/**
+ * CRISCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A CRIS CPU model.
+ */
+typedef struct CRISCPUClass {
+    /*< private >*/
+    CPUClass parent_class;
+    /*< public >*/
+
+    void (*parent_reset)(CPUState *cpu);
+
+    uint32_t vr;
+} CRISCPUClass;
+
+/**
+ * CRISCPU:
+ * @env: Legacy CPU state.
+ *
+ * A CRIS CPU.
+ */
+typedef struct CRISCPU {
+    /*< private >*/
+    CPUState parent_obj;
+    /*< public >*/
+
+    CPUCRISState env;
+} CRISCPU;
+
+static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
+{
+    return CRIS_CPU(container_of(env, CRISCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
+
+
+#endif
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
new file mode 100644
index 0000000..01bce90
--- /dev/null
+++ b/target-cris/cpu.c
@@ -0,0 +1,144 @@
+/*
+ * QEMU CRIS CPU
+ *
+ * Copyright (c) 2008 AXIS Communications AB
+ * Written by Edgar E. Iglesias.
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+#include "mmu.h"
+
+static void cris_cpu_reset(CPUState *c)
+{
+    CRISCPU *cpu = CRIS_CPU(c);
+    CRISCPUClass *klass = CRIS_CPU_GET_CLASS(cpu);
+    CPUCRISState *env = &cpu->env;
+
+    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+        qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+        log_cpu_state(env, 0);
+    }
+
+    klass->parent_reset(c);
+
+    memset(env, 0, offsetof(CPUCRISState, breakpoints));
+    env->pregs[PR_VR] = klass->vr;
+    tlb_flush(env, 1);
+
+#if defined(CONFIG_USER_ONLY)
+    /* start in user mode with interrupts enabled.  */
+    env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
+#else
+    cris_mmu_init(env);
+    env->pregs[PR_CCS] = 0;
+#endif
+}
+
+/* CPU models */
+
+typedef struct CRISCPUInfo {
+    const char *name;
+    uint32_t vr;
+} CRISCPUInfo;
+
+static const CRISCPUInfo cris_cpus[] = {
+    {
+        .name = "crisv8",
+        .vr = 8,
+    },
+    {
+        .name = "crisv9",
+        .vr = 9,
+    },
+    {
+        .name = "crisv10",
+        .vr = 10,
+    },
+    {
+        .name = "crisv11",
+        .vr = 11,
+    },
+    {
+        .name = "crisv32",
+        .vr = 32,
+    },
+};
+
+static void cris_cpu_initfn(Object *obj)
+{
+    CRISCPU *cpu = CRIS_CPU(obj);
+    CRISCPUClass *klass = CRIS_CPU_GET_CLASS(cpu);
+    CPUCRISState *env = &cpu->env;
+
+    memset(env, 0, sizeof(*env));
+    cpu_exec_init(env);
+    env->cpu_model_str = object_get_typename(obj);
+
+    env->pregs[PR_VR] = klass->vr;
+
+    cpu_reset(CPU(cpu));
+}
+
+static void cris_cpu_class_init(ObjectClass *klass, void *data)
+{
+    CPUClass *cpu_class = CPU_CLASS(klass);
+    CRISCPUClass *k = CRIS_CPU_CLASS(klass);
+    const CRISCPUInfo *info = data;
+
+    k->parent_reset = cpu_class->reset;
+    cpu_class->reset = cris_cpu_reset;
+
+    k->vr = info->vr;
+}
+
+static void cpu_register(const CRISCPUInfo *info)
+{
+    TypeInfo type = {
+        .name = info->name,
+        .parent = TYPE_CRIS_CPU,
+        .instance_size = sizeof(CRISCPU),
+        .instance_init = cris_cpu_initfn,
+        .class_size = sizeof(CRISCPUClass),
+        .class_init = cris_cpu_class_init,
+        .class_data = (void *)info,
+    };
+
+    type_register_static(&type);
+}
+
+static const TypeInfo cris_cpu_type_info = {
+    .name = TYPE_CRIS_CPU,
+    .parent = TYPE_CPU,
+    .instance_size = sizeof(CRISCPU),
+    .abstract = true,
+    .class_size = sizeof(CRISCPUClass),
+};
+
+static void cris_cpu_register_types(void)
+{
+    int i;
+
+    type_register_static(&cris_cpu_type_info);
+    for (i = 0; i < ARRAY_SIZE(cris_cpus); i++) {
+        cpu_register(&cris_cpus[i]);
+    }
+}
+
+type_init(cris_cpu_register_types)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 31899c2..5449cc4 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -169,6 +169,8 @@ typedef struct CPUCRISState {
 	void *load_info;
 } CPUCRISState;
 
+#include "cpu-qom.h"
+
 CPUCRISState *cpu_cris_init(const char *cpu_model);
 int cpu_cris_exec(CPUCRISState *s);
 void cpu_cris_close(CPUCRISState *s);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 7224f46..4097ecd 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3470,50 +3470,63 @@ void cpu_dump_state (CPUCRISState *env, FILE *f, fprintf_function cpu_fprintf,
 
 }
 
-struct
-{
-    uint32_t vr;
-    const char *name;
-} cris_cores[] = {
-	{8, "crisv8"},
-	{9, "crisv9"},
-	{10, "crisv10"},
-	{11, "crisv11"},
-	{32, "crisv32"},
-};
+typedef struct CRISCPUListState {
+    fprintf_function cpu_fprintf;
+    FILE *file;
+} CRISCPUListState;
 
-void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+/* Sort by version. */
+static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
 {
-    unsigned int i;
+    CRISCPUClass *class_a = CRIS_CPU_CLASS(a);
+    CRISCPUClass *class_b = CRIS_CPU_CLASS(b);
 
-    (*cpu_fprintf)(f, "Available CPUs:\n");
-    for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
-        (*cpu_fprintf)(f, "  %s\n", cris_cores[i].name);
+    if (class_a->vr == class_b->vr) {
+        return 0;
+    } else if (class_a->vr > class_b->vr) {
+        return 1;
+    } else {
+        return -1;
     }
 }
 
-static uint32_t vr_by_name(const char *name)
+static void cris_cpu_list_entry(gpointer data, gpointer user_data)
 {
-    unsigned int i;
-    for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
-        if (strcmp(name, cris_cores[i].name) == 0) {
-            return cris_cores[i].vr;
-        }
-    }
-    return 32;
+    ObjectClass *klass = data;
+    CRISCPUListState *s = user_data;
+
+    (*s->cpu_fprintf)(s->file, "  %s\n",
+                      object_class_get_name(klass));
 }
 
-CPUCRISState *cpu_cris_init (const char *cpu_model)
+void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 {
-	CPUCRISState *env;
+    CRISCPUListState s = {
+        .file = f,
+        .cpu_fprintf = cpu_fprintf,
+    };
+    GSList *list;
+
+    list = object_class_get_list(TYPE_CRIS_CPU, false);
+    list = g_slist_sort(list, cris_cpu_list_compare);
+    (*cpu_fprintf)(f, "Available CPUs:\n");
+    g_slist_foreach(list, cris_cpu_list_entry, &s);
+    g_slist_free(list);
+}
+
+CPUCRISState *cpu_cris_init(const char *cpu_model)
+{
+    CRISCPU *cpu;
+    CPUCRISState *env;
 	static int tcg_initialized = 0;
 	int i;
 
-	env = g_malloc0(sizeof(CPUCRISState));
+    if (object_class_by_name(cpu_model) == NULL) {
+        return NULL;
+    }
+    cpu = CRIS_CPU(object_new(cpu_model));
+    env = &cpu->env;
 
-	env->pregs[PR_VR] = vr_by_name(cpu_model);
-	cpu_exec_init(env);
-    cpu_state_reset(env);
 	qemu_init_vcpu(env);
 
 	if (tcg_initialized)
@@ -3575,25 +3588,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
 
 void cpu_state_reset(CPUCRISState *env)
 {
-	uint32_t vr;
-
-	if (qemu_loglevel_mask(CPU_LOG_RESET)) {
-		qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
-		log_cpu_state(env, 0);
-	}
-
-	vr = env->pregs[PR_VR];
-	memset(env, 0, offsetof(CPUCRISState, breakpoints));
-	env->pregs[PR_VR] = vr;
-	tlb_flush(env, 1);
-
-#if defined(CONFIG_USER_ONLY)
-	/* start in user mode with interrupts enabled.  */
-	env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
-#else
-	cris_mmu_init(env);
-	env->pregs[PR_CCS] = 0;
-#endif
+    cpu_reset(ENV_GET_CPU(env));
 }
 
 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
-- 
1.7.7

  parent reply	other threads:[~2012-03-14 17:54 UTC|newest]

Thread overview: 173+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
2012-03-05  9:23   ` Avi Kivity
2012-03-10  1:35     ` Andreas Färber
2012-03-12 10:36       ` Avi Kivity
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 2/3] qom: Register QOM infrastructure early Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators Andreas Färber
2012-03-07 14:11   ` Luiz Capitulino
2012-03-10  2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset() Andreas Färber
2012-03-13 18:02     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState Andreas Färber
2012-03-13 18:02     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions Andreas Färber
2012-03-13 18:03     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State Andreas Färber
2012-03-13 18:04     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 06/44] target-microblaze: Typedef struct CPUMBState Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 07/44] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State Andreas Färber
2012-03-13 18:05     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes Andreas Färber
2012-03-13 18:07     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState Andreas Färber
2012-03-13 18:08     ` Anthony Liguori
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 11/44] darwin-user: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 12/44] bsd-user: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: " Andreas Färber
2012-03-13 18:10     ` Anthony Liguori
2012-03-14 20:50       ` Andreas Färber
2012-03-14 20:58         ` Peter Maydell
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 14/44] target-arm: " Andreas Färber
2012-03-14 14:39     ` Peter Maydell
2012-03-14 18:33       ` Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 15/44] target-cris: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 16/44] target-i386: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 17/44] target-lm32: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 18/44] target-m68k: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 19/44] target-microblaze: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 20/44] target-mips: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 21/44] target-ppc: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 22/44] target-s390x: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 23/44] target-sh4: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 24/44] target-sparc: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 25/44] target-unicore32: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 26/44] target-xtensa: " Andreas Färber
2012-03-10  2:27   ` [Qemu-devel] [PATCH RFC v4 27/44] arm-semi: Don't use CPUState Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 28/44] m68k-semi: " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 29/44] xtensa-semi: " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 30/44] alpha hw/: " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 31/44] arm " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 32/44] cris " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 33/44] i386 " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 34/44] lm32 " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 35/44] m68k " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 36/44] microblaze " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 37/44] mips " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 38/44] ppc " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 39/44] s390x " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 40/44] sh4 " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 41/44] sparc " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 42/44] xtensa " Andreas Färber
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState Andreas Färber
2012-03-13 18:06     ` Andreas Färber
2012-03-13 18:11       ` Anthony Liguori
2012-03-10  2:28   ` [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class Andreas Färber
2012-03-12  9:38     ` Igor Mammedov
2012-03-13 12:13       ` Andreas Färber
2012-03-13 12:20         ` Paolo Bonzini
2012-03-13 12:53           ` Andreas Färber
2012-03-13 13:03             ` Paolo Bonzini
2012-03-13 18:16           ` Anthony Liguori
2012-03-14 20:37         ` Igor Mitsyanko
2012-03-14 19:48           ` Anthony Liguori
2012-03-14 19:57             ` Andreas Färber
2012-03-14 20:01               ` Anthony Liguori
2012-03-14 20:37           ` Andreas Färber
2012-03-14 20:40             ` Anthony Liguori
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list() Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass Andreas Färber
2012-03-13 12:31     ` Igor Mitsyanko
2012-03-13 17:58       ` Andreas Färber
2012-03-13 18:04         ` Eric Blake
2012-03-13 18:09           ` Eric Blake
2012-03-13 18:05         ` Paolo Bonzini
2012-03-13 18:12         ` Peter Maydell
2012-03-14  8:58         ` Igor Mitsyanko
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
2012-03-13 13:18     ` Paolo Bonzini
2012-03-14 22:30       ` Andreas Färber
2012-03-15  9:43         ` Paolo Bonzini
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 04/20] target-arm: Prepare model-specific class_init function Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState Andreas Färber
2012-03-15 18:56     ` Paul Brook
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
2012-03-15 19:08     ` Paul Brook
2012-03-15 19:20       ` Peter Maydell
2012-03-15 19:29         ` Alexey Starikovskiy
2012-03-15 19:42           ` Peter Maydell
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 11/20] target-arm: Drop JTAG_ID documentation Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 12/20] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 14/20] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 16/20] target-arm: Store CCSIDRs " Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id() Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes Andreas Färber
2012-03-10 16:53   ` [Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU Andreas Färber
2012-03-13 19:52 ` [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Anthony Liguori
2012-03-14  1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
2012-03-14  7:44     ` Guan Xuetao
2012-03-14  1:39   ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
2012-03-14  7:53     ` Guan Xuetao
2012-03-14 10:46       ` Andreas Färber
2012-03-14 20:03     ` Blue Swirl
2012-03-14 21:09     ` Stefan Weil
2012-03-14 21:20       ` Anthony Liguori
2012-03-14  1:39   ` [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU Andreas Färber
2012-03-14  7:56     ` Guan Xuetao
2012-03-14 10:56       ` Andreas Färber
2012-03-15  1:04         ` Guan Xuetao
2012-03-14  1:39   ` [Qemu-devel] [PATCH 4/7] target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys " Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags " Andreas Färber
2012-03-14  1:39   ` [Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr " Andreas Färber
2012-03-14  7:32   ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Guan Xuetao
2012-03-23 16:53     ` Andreas Färber
2012-03-14 20:02   ` Blue Swirl
2012-03-14 23:23     ` Anthony Liguori
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 05/12] target-sh4: Make increment_urc() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() " Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU Andreas Färber
2012-03-14 16:01   ` [Qemu-devel] [PATCH RFC 12/12] hw/sh7750: QOM'ify SH7750 SoC Andreas Färber
2012-03-14 16:06   ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and " Peter Maydell
2012-03-14 18:25     ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 03/12] target-m68k: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 04/12] target-alpha: " Andreas Färber
2012-03-14 17:59     ` Richard Henderson
2012-03-14 17:53   ` [Qemu-devel] [RFC 05/12] target-i386: " Andreas Färber
2012-03-15 19:30     ` Eduardo Habkost
2012-03-14 17:53   ` [Qemu-devel] [RFC 06/12] target-ppc: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 07/12] target-ppc: Prepare finalizer for PowerPCCPU Andreas Färber
2012-03-14 17:53   ` Andreas Färber [this message]
2012-03-14 17:53   ` [Qemu-devel] [RFC 09/12] target-lm32: QOM'ify CPU Andreas Färber
2012-03-15 22:42     ` Michael Walle
2012-03-14 17:53   ` [Qemu-devel] [RFC 10/12] target-microblaze: " Andreas Färber
2012-03-14 17:53   ` [Qemu-devel] [RFC 11/12] target-sparc: " Andreas Färber
2012-03-14 20:16     ` Blue Swirl
2012-03-23 17:27       ` Andreas Färber
2012-03-24 13:19         ` Blue Swirl
2012-03-14 17:53   ` [Qemu-devel] [RFC 12/12] target-xtensa: " Andreas Färber
2012-03-15 22:10     ` jcmvbkbc
2012-03-15 23:10       ` Max Filippov

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1331747617-7837-9-git-send-email-afaerber@suse.de \
    --to=afaerber@suse.de \
    --cc=edgar.iglesias@gmail.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).